Sony · Filed May 23, 2025 · Published Jul 9, 2026 · verified — real USPTO data

Sony Patents a Way to Stop AI Chips from Running Out of Room Mid-Calculation

Running AI on a small chip is a constant tug-of-war between speed and memory. Sony has a new patent that tries to ease that tension by compressing the data an AI model generates mid-calculation, then unpacking it exactly when the chip needs it again.

Sony Patent: Compressing AI Data Mid-Calculation to Save Memory — figure from US 2026/0197476 A1
Figure from the official USPTO publication.
Publication number US 2026/0197476 A1
Applicant Sony Semiconductor Solutions Corporation
Filing date May 23, 2025
Publication date Jul 9, 2026
Inventors Takefumi Nagumo, Takuya Kitamura, Yoshinori Ono, Atsushi Yamato
CPC classification 382/156
Grant likelihood Medium
Examiner CENTRAL, DOCKET (Art Unit OPAP)
Status Docketed New Case - Ready for Examination (Apr 7, 2026)
Parent application is a National Stage Entry of PCTJP2023044343 (filed 2023-12-12)
Document 27 claims

What Sony's mid-inference compression actually does

Imagine your phone's camera is running an AI model to recognize faces or detect objects in real time. As that AI works, it produces a huge amount of intermediate results, like rough sketches it made before reaching its final answer. Normally those rough sketches have to sit in memory, taking up a lot of space, until the AI needs them again a fraction of a second later.

Sony's patent describes a chip that compresses those in-progress results while they're waiting in memory, then automatically decompresses them the moment the AI is ready to use them. Crucially, the chip figures out the best compression plan before the AI even starts running, so there's no fumbling around mid-calculation.

The practical effect is that a smaller, cheaper memory chip could handle the same AI workload, or the same memory chip could handle a bigger, more capable AI model. That's a useful trade-off for anything battery-powered or space-constrained, like a camera sensor, a drone, or a wearable.

How the pre-analysis unit controls compression and decoding

The patent centers on four cooperating components inside a single processor or chip complex:

  • Preliminary analysis unit: Before inference (the process of running an AI model on real data) even begins, this unit examines the neural network's structure and figures out which intermediate values, called feature amounts, will be large, which will be needed soon, and which can safely be compressed aggressively. It writes those decisions into a set of control information rules.
  • Computing unit: The main AI engine. It runs the neural network layer by layer on incoming data, producing feature amounts as it goes. These are the intermediate tensors (grids of numbers) that represent partially processed information.
  • Compression unit: Intercepts feature amounts coming out of the computing unit and compresses them according to the pre-generated control information before writing them to memory. The compression strategy can vary layer by layer because the control information was tailored to the network's specific shape.
  • Decoding unit: When the computing unit needs a stored feature amount again, the decoder retrieves the compressed version from memory and restores it in time for the next calculation pass.

The key insight is that the compression parameters are decided ahead of time rather than at runtime, which keeps the process fast and predictable.

What this means for AI chips in cameras and edge devices

For Sony, whose semiconductor division makes image sensors and AI-accelerating chips used in cameras, smartphones, and automotive systems, keeping memory bandwidth low is a direct cost and power concern. Less memory traffic means lower power consumption, which matters a lot in always-on devices like security cameras or automotive sensor arrays. This kind of on-chip compression could let Sony sell capable AI inference chips that pair with smaller, cheaper DRAM.

For you as a user, the benefit is indirect: devices that do more AI processing locally (on the chip, not in the cloud) without draining the battery as fast. Think faster computational photography, real-time object detection in dashcams, or more responsive AR features on a headset, all without needing a bigger battery or a cloud connection.

Editorial take

This is solid, unglamorous chip engineering. The idea of compressing neural network activations to reduce memory pressure is a known research direction, and Sony's contribution here is a pre-analysis step that picks compression settings before inference starts, rather than making costly decisions on the fly. It's the kind of incremental but real improvement that shows up in product specs as lower power draw or support for larger AI models, not as a flashy headline feature.

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Source. Full patent text and figures from the official USPTO publication PDF.

Editorial commentary on a publicly published patent application. Not legal advice.