Qualcomm Patents a More Efficient Way for AI Chips to Handle Complex Math

By Patentlyze Team · Updated Jul 24, 2026

AI chips spend a surprising amount of energy doing complex math that could be approximated more cheaply. Qualcomm's new patent describes a smarter allocation scheme that could let AI hardware do more with less silicon.

What Qualcomm's adaptive math shortcut actually does

Imagine you're giving directions and you know some stretches of the route are tricky (lots of turns, traffic lights) while others are simple (straight highway). You'd naturally spend more words describing the complicated parts and fewer on the easy bits. Qualcomm's patent applies that same logic to math inside AI chips.

When a chip runs an AI model, it constantly evaluates complex mathematical functions (like the curves that decide whether a neuron fires). Computing those exactly is expensive, so chips use approximations built from simpler polynomial building blocks (think: lots of short straight-line segments stitched together to trace a curve). Most approaches spread those building blocks evenly across the whole curve, even the boring flat parts.

Qualcomm's approach is to concentrate more building blocks where the curve is complicated and use fewer where it's straightforward. That means you get better accuracy without throwing extra hardware at the whole problem.

How the non-uniform polynomial allocation works

The patent describes a three-step process for approximating non-linear functions (curved mathematical relationships) using linear polynomials (simpler, straight-line math that hardware handles cheaply).

• Segmenting: The full range of possible input values is split into many small intervals called "input segments", similar to dividing a number line into buckets.
• Slicing: Those segments are grouped into broader "slices," where each slice covers a different region of the input range.
• Non-uniform allocation: Here's the key idea. Instead of assigning the same number of polynomial approximations to every slice, the system assigns more polynomials to slices where the function changes rapidly (high curvature) and fewer to slices where it barely changes. This is the "non-uniform" part.

The result is that the chip's lookup tables and compute units are used where they matter most. The patent covers both the allocation strategy and the actual computation step that uses those polynomials to evaluate the function at runtime. This kind of optimization is especially relevant for AI accelerators (dedicated chips that run neural networks) because operations like GELU, sigmoid, and softmax (common activation functions in large language models) are non-linear and must be evaluated billions of times per second.

What this means for on-device AI performance

On-device AI, whether in a phone, a car, or a wireless modem, runs on tight power and area budgets. Every bit of compute efficiency translates directly into longer battery life, faster inference, or the ability to run a larger model in the same envelope. Qualcomm supplies the chips inside billions of Android phones and many automotive and IoT systems, so optimizations at this level can ripple across a huge installed base.

This patent sits squarely in the category of hardware math unit design, the kind of foundational work that rarely makes headlines but determines whether a given chip generation can run the next wave of AI models at acceptable speed and power. If this technique ships in a Snapdragon or AI 100 series chip, you'd feel it as smoother AI features with less heat and fewer charging interruptions, even if you'd never know why.

Editorial commentary on a publicly published patent application. Not legal advice.