Samsung Patents a Taller-Stack Method for Building 3D Flash Memory Chips

By Patentlyze Team · Updated Jun 12, 2026

Fitting more storage into the same tiny chip footprint is one of the hardest problems in consumer electronics — and Samsung's latest patent describes a precise manufacturing method for stacking memory layers higher without the whole structure collapsing or misfiring.

What Samsung's stacked memory chip design actually does

Think of a NAND flash memory chip — the kind that stores your photos, apps, and files on an iPhone or SSD — as a skyscraper. The more floors you can build, the more data you can store in the same floor plan. But building taller creates real engineering headaches: the holes you drill through dozens of layers to connect everything have to line up perfectly, or the chip doesn't work.

Samsung's patent describes a way to build that skyscraper in two separate construction phases. You build the lower half first, punch the necessary holes, then build the upper half on top and connect everything through. A support structure holds the upper section steady while the connections are made.

The result is a chip where the storage cells, their electrical pathways, and the insulating walls between them all maintain the precise geometry needed to work reliably — even as the total number of layers keeps climbing. It's painstaking plumbing work, but it's the kind that makes denser, cheaper flash storage possible.

How Samsung layers and etches the dual-stack structure

This patent covers a manufacturing process for building a 3D NAND flash memory device — the type of chip used in SSDs, smartphones, and USB drives — using a two-phase stacking approach.

The first phase builds a lower preliminary stack: alternating layers of sacrificial insulating material and permanent interlayer insulation. Holes are etched down through this lower stack — channel holes (where the actual memory cells will live) and separation holes (which will eventually become the isolation walls dividing memory blocks). At this stage, the sacrificial layers are placeholders that will later be replaced by the actual metal gate electrodes that control each memory cell.

The second phase deposits an upper preliminary stack directly on top, using the same alternating-layer recipe. New holes are etched through the upper stack and carefully aligned to connect with the ones below. A support structure is then formed over the entire upper stack to keep it mechanically stable during subsequent processing steps.

Finally, through-regions are opened in the support structure, connecting down into the separation holes — allowing the sacrificial material to be chemically removed and replaced with conductive gate electrodes in a later step. A notable geometric detail: the isolation structures that run through the full stack have a narrower top surface on the middle segment than the bottom surface of the upper segment, a shape that results naturally from the two-phase etch process and helps each section stay properly aligned.

What this means for flash storage density and cost

Every generation of 3D NAND flash has to stack more layers to stay competitive on cost-per-gigabyte. Samsung, SK Hynix, and Micron are all racing past 200 layers, and the two-phase build approach described here is one of the main engineering strategies for getting there without yield losses that make the chips too expensive to sell. A patent on a specific stacking geometry and support-structure method could represent a proprietary manufacturing process that gives Samsung a yield or density edge.

For you as a consumer, this kind of incremental manufacturing work is what eventually shows up as cheaper SSDs and higher-capacity phone storage. It's not glamorous, but it's the engineering that moves the needle on the specs you actually buy.

Editorial commentary on a publicly published patent application. Not legal advice.