Xilinx Patents an AI Chip Multiplier That Handles More Number Formats Than Usual

By Patentlyze Team · Updated Jul 21, 2026

Most AI chips are built to crunch numbers in one specific format. Xilinx is patenting a multiplier that can handle a wider range of number types in the same piece of silicon.

What Xilinx's expanded number-format chip actually does

Imagine you have a calculator that only works with whole numbers. If someone hands you a problem involving fractions or very large decimals, you're stuck. AI chips face a similar constraint: they're usually built to process one specific kind of number format, and switching to a different format can mean redesigning the hardware.

Xilinx is patenting a multiplier (the part of a chip that does multiplication) that natively supports what the patent calls a "superset" of a standard number format. In plain terms, it can handle numbers that are bigger or more precise than the format it's officially built for, without needing a separate piece of hardware to do it.

The number format in question is called floating-point, which is how computers store decimal numbers with varying precision. By extending what the multiplier can handle, the same chip can process a broader range of AI calculations without extra circuitry or workarounds.

How the multiplier stretches beyond standard floating-point limits

The patent describes an AI engine built around a register file (a small, fast bank of memory that holds numbers being actively processed) and a multiplier that supports a "superset" of a floating-point data type.

Floating-point is the standard way computers represent decimal numbers. Each floating-point number has two key parts: a mantissa (the significant digits, like the "1.5" in "1.5 × 10²") and an exponent (the scale, like the "2"). Standard chips are built to a fixed maximum for both parts.

This patent extends both limits. The multiplier can handle:

• A larger maximum mantissa value (more significant digits, meaning more precision)
• A larger maximum exponent value (bigger or smaller numbers without overflow)

Additionally, the register file stores multiple variants of the same data type, and there is dedicated logic to expand multiplication operations beyond their normal range. The net effect is that one physical multiplier covers more numerical ground than a conventional design, reducing the need for separate hardware paths when switching between AI workloads that use different number precisions.

What this means for AI chip flexibility and AMD's roadmap

AI training and inference increasingly mix different number formats. A model might use lower-precision numbers to save memory, then switch to higher precision for accuracy-critical steps. Today, that often means either accepting errors or designing multiple hardware blocks. A multiplier that natively covers a superset of a format could reduce that hardware overhead.

Xilinx is now part of AMD, which uses Xilinx's programmable chip technology (FPGAs) in data center AI accelerators. A more flexible multiplier could make those chips more attractive for AI workloads that don't fit neatly into a single number format, giving AMD's AI hardware a practical edge in adaptability over fixed-function competitors.

Editorial commentary on a publicly published patent application. Not legal advice.