AMD Patents a Way to Make Broken Data Center Chips Point to Themselves

Publication number

US 2026/0170592 A1(US20260170592A1)

Applicant

ATI Technologies ULC

Filed · Published

Dec 17, 2024 · Jun 18, 2026

Inventors

Ting-Yu Lin

Status when we published

Examiner raised objections; the company can respond

Document

20 claims

US classification

345/501

Examiner

CHEN, BIAO (Art Unit 2611)

What ATI's GPU location numbering actually does

Imagine a warehouse with hundreds of identical boxes stacked in rows and columns, and someone tells you 'Box 47 is broken.' Without a floor map, you'd have no idea where Box 47 actually sits. That's exactly the problem data centers face when a GPU fails — the chip has an ID, but nothing in that ID tells you where it physically lives in the rack.

ATI's patent fixes this by making the ID number do double duty. Instead of a generic serial-style number, each GPU gets an index that encodes its row and column position inside the server. So when a monitoring system flags a problem, the ID itself tells the technician exactly where to walk and which chip to pull.

The goal is faster repairs with fewer mistakes. Right now, technicians often have to cross-reference system diagrams just to locate a single bad chip. This patent would make the chip's ID its own address label, cutting out that lookup step entirely.

How index numbers encode a GPU's physical position

The patent describes a system where indexer circuitry (a dedicated hardware block) assigns each GPU in a server an index number that encodes its physical position — think of it like a grid coordinate baked into the chip's ID.

The GPUs are arranged in a two-dimensional grid inside the server. The indexer reads the physical layout and generates index numbers that reflect each unit's row and column in that grid. So instead of a flat list like GPU-0 through GPU-63, you might get IDs that tell you 'row 3, column 5' directly.

Key components described in the patent include:

• Multiple accelerator units (GPUs) arranged in a fixed physical configuration
• Indexer circuitry that enumerates each unit at system startup or configuration time
• Index identifiers structured to encode position, not just sequence order

When a monitoring system detects a failing GPU and reports its index, that index number alone tells the technician where to go — no schematics, no secondary lookup tools required.

What this means for data center repair times

Data centers — especially the AI training clusters that now pack thousands of GPUs into dense racks — spend real money on downtime caused by slow fault diagnosis. When a single GPU fails in a cluster of hundreds, every minute spent hunting for it is compute time lost. A system that makes the chip's ID its own address could meaningfully cut mean-time-to-repair.

For AMD and ATI, whose GPUs are increasingly deployed in large-scale AI infrastructure alongside Nvidia's, operational efficiency at the data center level is a real selling point. If ATI hardware is easier to service than a competitor's, that's a concrete advantage when a hyperscaler is evaluating which chips to fill a rack with.

Source: US 2026/0170592 A1 at the USPTO (PDF). Full patent text and figures are in the official publication.

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