Chip Designer AMD Patents an AI Processor That Runs Two Types of Math at Once

By Patentlyze Team · Updated Jul 21, 2026

Most AI chips do one heavy calculation at a time and then move on. Xilinx's new patent describes a chip design where two different kinds of math run side by side, at the same moment, on dedicated circuits built for each job.

What Xilinx's parallel AI engine actually does

Imagine a kitchen where one chef handles all the chopping and another handles all the cooking, both working at the same time instead of taking turns. That's roughly the idea here. AI calculations tend to fall into two broad categories: operations that crunch big grids of numbers (matrices) and operations that work through lists of numbers (vectors). Today's AI chips often handle these one after the other.

Xilinx's patent describes splitting those two jobs onto separate circuits inside the same chip, so they run at the same time. The matrix circuit does its grid math while the vector circuit independently handles its list math, without either one waiting on the other.

The practical result is that the chip gets through more work in the same amount of time, which is important because the AI models running on these chips are getting bigger and more demanding every year.

How the two circuits split and share the work

The patent describes an AI engine built around two distinct pieces of circuitry working in parallel:

• First functional circuitry: dedicated to matrix operations, meaning calculations that multiply or otherwise combine two-dimensional grids of numbers. This is the core math behind most neural network layers.
• Second functional circuitry: dedicated to vector operations, meaning calculations on one-dimensional lists of numbers. These often handle tasks like applying an activation function (a step that shapes the output of a neural network layer) or scaling values.

The key word in the patent is concurrently. The two sets of instructions execute at the same time rather than in sequence. A traditional design would finish the matrix work, then start the vector work. This design keeps both circuits busy simultaneously.

The patent also covers a mixed case: the matrix circuitry can operate on a matrix combined with a vector (a common operation in AI inference), while the vector circuitry independently handles a separate vector task at the same time. That overlap is where the efficiency gains come from.

What this means for AI chip efficiency

In AI hardware, idle time is wasted power and wasted money. If a chip's vector unit sits doing nothing while the matrix unit finishes its work, that's a real cost at scale, especially for data centers running AI models continuously. By keeping both circuits busy at once, Xilinx's design squeezes more operations per second out of the same silicon.

Xilinx (now part of AMD) specializes in FPGAs, chips that can be reprogrammed for specific tasks. An AI engine that parallelizes matrix and vector math neatly fits into the company's push to make its programmable chips competitive with dedicated AI accelerators from Nvidia and Google. This kind of architectural efficiency, though unglamorous, is often what separates winning silicon from also-rans.

Editorial commentary on a publicly published patent application. Not legal advice.