Xilinx Patents a Processor That Loans Its CPU Cores to an Accelerator on Demand

By Patentlyze Team · Updated Jul 21, 2026

Most chips draw a hard line between the CPU and the accelerator. Xilinx's new patent erases that line, letting the processor hand its own cores to the accelerator whenever the workload demands it.

How Xilinx's reassignable chiplets actually work

Imagine a restaurant kitchen where the prep cooks are permanently assigned to one station, no matter how busy the other stations get. That's roughly how today's chips work: the CPU has its own cores, the accelerator has its own, and the two sides never trade staff.

Xilinx's patent describes a different design. The processor is built from interchangeable blocks called chiplets, and a piece of software called a composable agent can reassign some of those blocks from the main CPU to the accelerator, turning them into a more powerful IO device whenever your application needs the extra muscle. When the heavy lifting is done, those blocks can return to regular CPU duty.

The practical payoff is that you stop paying the cost of idle hardware. A server running an AI inference job one hour and a database query the next doesn't need two fixed, half-used resource pools. It needs one flexible pool it can reshape on the fly.

How the composable agent splits and reassigns chiplets

The patent describes a processor system built on a single substrate that holds two types of chiplets: core complex chiplets (each containing one or more processor cores) and an accelerator chiplet.

A software layer called the composable agent is the key piece. It can take any subset of the core complex chiplets and assign them to the accelerator chiplet, which then presents itself to the rest of the system as an IO device (a self-contained peripheral, like a network card or a GPU, as far as the operating system is concerned). The remaining core complex chiplets continue operating as the host CPU.

• The split is dynamic: the composable agent decides the division based on what application is running.
• Hardware resources (memory controllers, interconnects, and compute cores) follow whichever side they're assigned to.
• Because all chiplets sit on the same substrate and share the same interconnect fabric, moving resources between CPU and accelerator avoids the latency penalty of crossing a chip-to-chip bus as you would with a discrete add-in card.

The design is explicitly aimed at workloads that shift in character over time, so the ratio of CPU work to accelerator work changes without replacing any physical hardware.

What this means for data center chip efficiency

For anyone buying or operating servers, the appeal is straightforward: you can buy one class of hardware and tune its behavior through software rather than stocking separate CPU-heavy and GPU-heavy machines for different jobs. That matters a lot in data centers where workloads are mixed and provisioning decisions are made months before anyone knows exactly what will run on the box.

For Xilinx (now part of AMD), this is also a pointed claim in the argument that FPGAs and adaptive accelerators belong inside the main processor complex, not bolted on as afterthoughts. If the patent reflects a real product direction, it suggests AMD-Xilinx is positioning chiplet-based flexibility as a direct answer to fixed-function accelerator cards from competitors.

Editorial commentary on a publicly published patent application. Not legal advice.