Intel Patents a Leaner Way to Store Numbers Inside AI Chips

By Patentlyze Team · Updated Jul 10, 2026

AI chips spend most of their time doing one thing: multiplying enormous tables of numbers together. Intel thinks it has found a cheaper way to pull that off by changing how numbers are stored in memory in the first place.

What Intel's bit-plane memory format actually does

Think of how your phone stores photos. It packs red, green, and blue values for every pixel in a neat row, one pixel at a time. Now imagine instead sorting all the red values together, then all the green, then all the blue. That reorganization sounds cosmetic, but it can make certain operations dramatically faster because the chip grabs exactly what it needs without wading through the rest.

Intel's patent does something similar for the numbers an AI processes. Instead of storing each value as a complete block of bits lined up in a row, it stores the numbers in bit plane format, which groups the same "position" of every number together. That lets the chip handle values of different sizes without wasted space, and it lets simpler circuits called adders do work that normally requires more power-hungry multiplier circuits.

The claimed payoff is faster AI processing and lower memory use. Whether that gap is big enough to matter in real products is the real question.

How adders replace multipliers in Intel's matrix engine

At the center of every AI model is a matrix multiplication, which is the process of multiplying large grids of numbers against each other millions of times per second. Normally, each number is stored as a fixed-width block of bits sitting one after another in memory. The chip's circuits are designed around that fixed layout, which means any variation in number size wastes space or requires extra bookkeeping.

Bit plane format flips the layout. Instead of storing all the bits for value A, then all the bits for value B, and so on, it groups bit position 0 from every value together, then bit position 1 from every value, and so on. This lets the chip mix values of different bit widths in the same memory space without padding or gaps.

The architectural benefit is that this layout is naturally suited to addition-based computation. The patent describes using adders (simpler, lower-power circuits) rather than the more expensive multiplier circuits that standard matrix engines rely on. In hardware terms, fewer transistors doing the same logical work means lower energy per operation and potentially higher throughput.

The key claims are:

• A processor with memory that stores data in bit plane format and uses adder arrays for matrix operations
• A full system pairing that memory and processor with a dedicated matrix multiplication module
• A method covering store, retrieve, and compute steps in the same format

What this means for AI chip efficiency at scale

AI training and inference are already straining data center power budgets, and chip designers are under pressure to do more math per watt. A memory layout that cuts waste while enabling simpler circuits is exactly the kind of low-level architectural bet that compounds over thousands of chips running in parallel. Intel is competing hard against Nvidia and AMD for AI accelerator market share, and efficiency gains at this level of the stack are a legitimate engineering lever.

For the average person, this kind of work is invisible but consequential. If it ships in real silicon, the AI assistant you talk to or the image generator you use could respond faster or cost less to run, without any change to the software you see.

Editorial commentary on a publicly published patent application. Not legal advice.