Xilinx Patents an AI Chip That Swaps Multipliers for Memory Lookups
Multiplication is one of the most power-hungry operations in any AI chip. Xilinx thinks it has found a way to do less of it, by doing the math once and looking up the answer every time after that.
What Xilinx's lookup-table AI engine actually does
Imagine you're a cashier who has to calculate 20% of every item a customer brings up. You could pull out a calculator each time, or you could make a quick cheat sheet at the start of your shift and just look up the answer. Xilinx's patent applies exactly that logic to AI chips.
AI processing involves enormous numbers of multiplications, billions of them per second. Those multiplications consume a lot of power. This patent describes a circuit that, instead of recalculating the same multiplication over and over, builds a small lookup table of pre-computed answers and then just reads from it repeatedly.
The trick works because one of the two numbers being multiplied, the "first operand" (think of it as a stored weight in a neural network), stays the same across many cycles. You do the math once to fill the table, then your chip just looks up results instead of grinding through fresh multiplications. That reduces how hard the chip has to work, and how much power it draws.
How the LUT pre-population and indexing cycle works
The patent describes an AI engine built around a specific shortcut in how multiplication works at the hardware level.
In a standard AI chip, multiplying two numbers together requires dedicated multiplier circuits, which are expensive in terms of silicon area and power. The Xilinx approach breaks one operand (a number in a calculation) into smaller chunks, then pre-computes all the partial products for those chunks against the second operand. Those pre-computed results are stored in a lookup table (LUT).
The key insight is that in AI workloads, one of the two numbers being multiplied, typically a model weight, stays constant across many operations while the other number (incoming data) changes. That pattern makes the lookup-table approach efficient:
- In the first cycle, the static operand fills the LUT with pre-computed values.
- In every following cycle, the changing operand is used as an index to retrieve the right answer from the table, rather than triggering a fresh multiplication.
- Memory accesses to the LUT are specifically designed to reduce power draw compared to running full multiplier hardware.
This is a classic hardware trade-off: swap compute (which uses power) for memory lookups (which, when designed carefully, use less). The patent claims efficiency gains specifically for AI inference workloads where weights are reused constantly.
What this means for AI chip power and performance
AI chips are locked in a war against power consumption. Data centers running large models pay enormous electricity bills, and edge devices like phones and embedded systems have strict battery budgets. Any technique that meaningfully reduces the energy cost of multiplication, the core arithmetic of neural networks, has real commercial value.
Xilinx (now part of AMD) makes FPGAs, which are chips whose logic can be reconfigured after manufacturing. LUTs are already a native building block of FPGAs, which makes this approach particularly natural for Xilinx hardware. If the technique delivers meaningful power savings at scale, it could show up in future AMD Versal or Alveo AI accelerator products aimed at data center inference workloads.
This is unglamorous but genuinely interesting chip architecture work. Replacing multipliers with lookup tables is a well-known idea in digital design, but applying it specifically to the static-weight property of AI inference workloads is a sensible and potentially impactful angle. Whether the power savings hold up at the scale of a real AI accelerator is the real question, and this patent doesn't answer it.
The drawings
6 drawing sheets from US 2026/0219838 A1 · click any drawing to enlarge
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Editorial commentary on a publicly published patent application. Not legal advice.