AMD Patents a Way to Let Programmers Control Number Scaling Inside AI Chips
When an AI chip does math with compressed numbers, tiny rounding errors can pile up fast. AMD is patenting a way to let programmers step in and manually tune how those numbers are scaled before the chip does its calculations.
What AMD's operand scaling control actually does
Imagine you're taking a high-resolution photo and squishing it down to fit on a floppy disk. You lose detail. AI chips do something similar when they compress numbers to run calculations faster. That compression introduces small errors, and when you're multiplying millions of numbers together, those errors can snowball.
AMD's patent describes a special storage slot inside the chip, called a scale register, that holds a collection of correction factors for both sets of numbers going into a calculation. Instead of the chip automatically picking which correction factor to use, the programmer can choose the right one manually.
The upshot: this gives developers fine-grained control over accuracy versus speed tradeoffs, which matters a lot when you're training or running large AI models where getting the math slightly wrong can mean the whole model performs worse.
How the scale register picks factors from stored sets
The patent centers on a scale register, a small, dedicated storage unit inside a processor that holds two collections of correction multipliers, one for each input going into a mathematical operation.
In AI workloads, numbers are often quantized (compressed from a high-precision format, like 32-bit floating point, down to a lower-precision format, like 8-bit integers) to save memory and speed up computation. Each compressed number loses some accuracy, so a scale factor is stored alongside it to help reconstruct approximately the original magnitude.
The key move in this patent is that the scale factor isn't chosen automatically by hardware. Instead, user input (meaning software or programmer instruction) selects which specific scale factor from the stored set gets applied. The patent pays particular attention to the outer product operation, a common matrix math building block used heavily in neural network layers, where one vector is multiplied against another to produce a full matrix of results.
- Scale register stores two sets of block scale factors, one per input vector
- A processing unit (including a matrix engine) applies the user-selected scale factors before computing
- The result is a matrix calculation that can be tuned for precision on the fly
What this means for AI training chip precision
AI chips already use quantization to run models faster, but they typically automate the precision tradeoffs. Giving developers direct control over scale factor selection means they can make deliberate choices about where accuracy matters most in a given layer or workload. That kind of manual tuning is something researchers and performance engineers have wanted but few chip architectures expose directly.
For AMD, this is relevant to its Instinct line of data center GPUs competing against Nvidia in AI training. Control over quantized math is one of the technical levers that can close gaps in model accuracy at a given speed, which is exactly the competition AMD needs to win in AI infrastructure.
This is a narrow but technically meaningful patent aimed squarely at AI chip engineers. It won't change how end users interact with anything, but it could give AMD a real edge with the researchers and infrastructure teams who tune large models by hand. The fact that it targets outer product operations, a core operation in transformer-based AI, signals this is designed for current workloads, not hypothetical ones.
The drawings
7 drawing sheets from US 2026/0220226 A1 · click any drawing to enlarge
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Editorial commentary on a publicly published patent application. Not legal advice.