Intel · Filed Dec 17, 2025 · Published Jun 11, 2026 · verified — real USPTO data

Intel Patents a Chip That Automatically Sends Tasks to the Right Processor

Modern chips don't just have one kind of processor anymore — they have several, each good at different jobs. Intel's new patent describes a hardware-level traffic controller that figures out which processor should handle which instruction, automatically, in real time.

Intel Patent: Heterogeneous Computing Chip Scheduler — figure from US 2026/0161441 A1
FIG. 1A — rendered from the official USPTO publication PDF.
Publication number US 2026/0161441 A1
Applicant Intel Corporation
Filing date Dec 17, 2025
Publication date Jun 11, 2026
Inventors Rajesh M. SANKARAN, Gilbert NEIGER, Narayan RANGANATHAN, Stephen R. VAN DOREN, Joseph NUZMAN, Niall D. MCDONNELL, Michael A. O'HANLON, Lokpraveen B. MOSUR, Tracy Garrett DRYSDALE, Eriko NURVITADHI, Asit K. MISHRA, Ganesh VENKATESH, Deborah T. MARR, Nicholas P. CARTER, Jonathan D. PEARCE, Edward T. GROCHOWSKI, Richard J. GRECO, Robert VALENTINE, Jesus CORBAL, Thomas D. FLETCHER, Dennis R. BRADFORD, Dwight P. MANLEY, Mark J. CHARNEY, Jeffrey J. COOK, Paul CAPRIOLI, Koichi YAMADA, Kent D. GLOSSOP, David B. SHEFFIELD
CPC classification 712/3
Grant likelihood Medium
Examiner CENTRAL, DOCKET (Art Unit OPAP)
Status Docketed New Case - Ready for Examination (Mar 6, 2026)
Parent application is a Continuation of 18927065 (filed 2024-10-25)
Document 20 claims

What Intel's mixed-processor scheduling actually does

Imagine a busy restaurant kitchen where some cooks are great at grilling, others at baking, and others at salads. If the head chef has to personally direct every single task, things slow down fast. Intel's patent is essentially a self-managing head chef for a chip.

Modern processors — especially ones used for AI — bundle together different types of computing engines on a single piece of silicon. There might be a general-purpose CPU core sitting next to a specialized AI accelerator or a graphics-style unit. The problem is getting work to the right engine quickly, without a software layer getting in the way.

What Intel is patenting here is a hardware scheduler — a dedicated circuit that lives on the chip and automatically dispatches instructions to whichever processing engine is best suited to run them. The instructions don't need to be translated or rewritten; each engine gets code it understands natively, keeping things fast.

How the hardware dispatcher assigns instructions to the right core

At its core, this patent covers two related ideas bundled together under the umbrella of heterogeneous computing.

The first — described in the abstract — is a hardware heterogeneous scheduler: a circuit that sits between the chip's instruction stream and its various processing engines (CPU cores, AI accelerators, vector units, etc.) and decides in real time which engine should execute which chunk of code. Crucially, it dispatches native instructions — meaning each engine receives instructions already formatted for it, rather than requiring on-the-fly translation.

The second — described in the actual first independent claim, which is the legally operative part — is a specific multiply-and-accumulate (MAC) instruction. This is a fundamental math operation used constantly in AI and signal processing: take two lists of numbers (packed data operands, meaning multiple values bundled into a single wide register), multiply them element-by-element, sum the results, and add those sums into a running total stored in a destination register. In short:

  • Multiply matching elements across multiple data vectors
  • Sum all those products
  • Accumulate the result into a destination register

This kind of fused multiply-accumulate operation is the workhorse of neural network inference and matrix math. Having it encoded as a single hardware instruction — rather than many separate steps — cuts the number of operations the scheduler has to manage.

What this means for AI chips and data center workloads

For AI workloads, the multiply-accumulate loop Intel is patenting here is essentially the atomic unit of matrix multiplication — the math that powers every transformer model and neural network running today. Getting that operation implemented at the hardware instruction level, rather than relying on software libraries to stitch together smaller operations, is how chip makers squeeze out performance and energy efficiency.

The broader heterogeneous scheduling angle matters for Intel's competitive position. As AI accelerators, CPUs, and specialized cores increasingly share the same package, the chip that manages traffic between them most efficiently wins on benchmark numbers and real-world throughput. This patent stakes Intel's claim to doing that coordination in hardware rather than leaving it to the operating system or a software runtime.

Editorial take

This is a dense, technically deep filing that bundles a broad architectural concept (heterogeneous scheduling) with a very specific instruction-set detail (a wide multiply-accumulate operation). The MAC instruction claim is the more concrete and defensible piece — it's the kind of low-level hardware building block that quietly shapes how AI inference chips perform for years. Don't expect a press release about this one, but it's the kind of foundational work that matters.

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Source. Full patent text and figures from the official USPTO publication PDF.

Editorial commentary on a publicly published patent application. Not legal advice.