Intel · Filed Mar 27, 2026 · Published Aug 6, 2026 · verified — real USPTO data

Intel Patents a System That Splits AI Training Across Two Different Chip Types

Training a large language model is one of the most expensive computing jobs on the planet. Intel's new patent proposes splitting that job across two fundamentally different types of chips, each doing what it does best, and then passing the results back and forth in real time.

Intel Patent: LLM Reinforcement Learning With Mixed Chips — figure from US 2026/0228552 A1
Figure from the official USPTO publication.
See all 6 drawings from this filing ↓
Publication number US 2026/0228552 A1
Applicant Intel Corporation
Filing date Mar 27, 2026
Publication date Aug 6, 2026
Inventors Yang Wang, Ke Ding, Chendi Xue, Daniel Huang
CPC classification 706/16
Grant likelihood Medium
Examiner CENTRAL, DOCKET (Art Unit OPAP)
Status Prosecution Suspended/Delayed (Jun 3, 2026)
Document 20 claims

How Intel splits AI training across two chip types

Imagine a bakery where one team does nothing but taste-test bread all day, and a second team uses that feedback to adjust the recipe. They hand notes back and forth constantly, each focused on their one job. Intel's patent describes something similar for AI training.

When companies build AI models like chatbots, there are two big jobs happening: the model generates answers (called inference), and then a separate process grades those answers and updates the model based on what was good or bad (called reinforcement learning). Right now, these two jobs often run on the same type of chip, even though they have very different demands.

Intel's approach is to run each job on a different type of processor, whichever hardware fits that task best, and then use a dedicated transfer system to send the updated model settings from the training chips back to the inference chips automatically. The goal is to keep both sides busy and reduce wasted computing time.

How the weight transfer engine links the two processor pools

The patent describes a system with three main components working together:

  • First processor pool (inference side): These chips run the AI model as it currently exists, generating outputs. In reinforcement learning terms, this is the model "acting in the world" and producing training data samples.
  • Second processor pool (training side): These chips have a different architecture from the first group, meaning they are a fundamentally different chip design, not just a faster version of the same thing. They take the outputs from the inference side, score them using a reward signal (the reinforcement learning step), and update the model's weights (the internal numerical settings that define how the model behaves).
  • Weight transfer engine: This is the connective tissue. It opens direct point-to-point communication channels between the two processor pools so the updated weights can be pushed from the training chips back to the inference chips without going through a slow central bottleneck.

The key architectural insight is that inference and reinforcement learning training have different computational profiles. Inference is often bottlenecked by memory bandwidth; training is bottlenecked by raw compute throughput. Using heterogeneous processors lets each workload land on better-suited hardware, rather than forcing both onto the same chip type.

We find one patent like this every day. Get the best of each week in your inbox, free →

What this means for AI training hardware costs

The AI industry is in an arms race over training efficiency, and the cost of running reinforcement learning from human feedback (the technique behind models like ChatGPT) is enormous. If Intel can show that mixing chip types, such as pairing its Gaudi AI accelerators with Xeon CPUs or other combinations, reduces idle time and cuts energy use during training runs, that is a real cost argument for cloud providers and enterprises building their own models.

For everyday users, this is infrastructure-level work that you would never see directly. But it feeds into how quickly AI companies can iterate on their models and at what cost, which eventually shows up in pricing and capability.

Editorial take

This is a solid, practical engineering patent rather than a flashy AI concept. Intel is targeting a real inefficiency in how AI training pipelines are built today, and the heterogeneous-processor angle fits Intel's product strategy of pushing customers toward mixed Gaudi-plus-Xeon deployments. Whether the weight transfer engine is novel enough to hold up against existing distributed training frameworks is the real question.

There are more where this came from

We read every patent application Big Tech publishes and send you the ones worth knowing. Plain English, free, every week.

The drawings

6 drawing sheets from US 2026/0228552 A1 · click any drawing to enlarge

Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.

Editorial commentary on a publicly published patent application. Not legal advice.