Nvidia · Filed Apr 21, 2025 · Published Nov 5, 2026

A New Nvidia Patent Reworks How Many Chips Share One Chatbot's Workload

Behind every chatbot answer, dozens of chips have to coordinate, and the chatter between them costs time. Nvidia's filing describes a way to cut that chatter with one simple swap, then put the same chips to work on a different job.

Rows of computers in a facility work together to run AI programs too large for a single machine. Drawing from patent filing US 2026/0350352 A1.
Rows of computers in a facility work together to run AI programs too large for a single machine.
See all 26 drawings from this filing ↓
Publication number US 2026/0350352 A1 US20260350352A1
Applicant NVIDIA Corporation
Filing date Apr 21, 2025
Publication date Nov 5, 2026
Inventors Nidhi Bhatia, Jian Liu, Bita Darvish Rouhani
US classification 706/15
Status when we published Waiting for an examiner (Jul 2, 2025)
Document 20 claims

What Nvidia's chip-sharing chatbot plan does

Ever been stuck in a group project where everyone finishes their part, then spends forever swapping notes before the next step? The computers that serve AI chatbots run into a version of that problem.

When thousands of people ask a chatbot questions at once, a data center spreads those requests across many chips. Those chips have to store each conversation's running memory and keep reloading the model's enormous set of learned numbers. Both jobs eat time, and passing results between chips eats more.

Nvidia's filing describes a way to divide the work in two stages. First, each chip handles its own share of the conversations. Then the chips make one simple swap of partial results, and each chip takes a different slice of the model's next stage. In the filing's worked example, that swap sends roughly 78% less data than a common alternative.

From the filing · CLAIM 1
receives a batch partition of the batch of input data to compute attention values for a Key-Value (KV) attention head partition that uses a KV cache of context data for the inferences …

Translation: The chip handles a specific slice of the workload using stored conversation history.

How the chips trade notes mid-calculation

A transformer (the design behind most chatbots) works in two stages. The first is attention, where the model works out which earlier words matter for the next one. The second is a feed-forward network, or FFN (a big block of learned numbers that enriches each word's representation). The patent covers running a batch of requests across several processors, such as GPUs, in a way that suits both stages.

In the first stage, each processor receives a slice of the batch and a slice of the KV attention heads (separate "viewpoints" the model uses to relate words). Each one also reads its matching piece of the KV cache, a stored record of earlier context so the model does not recompute it.

  • Split the batch and the attention heads across processors.
  • Compute attention values locally on each processor.
  • Swap results with an All-to-All exchange, where every processor sends data to every other one. No adding is involved, so lower-precision number formats such as 4-bit floating point can be used.
  • Compute the output, with each processor holding a different slice of the FFN weights.

The filing works through one example: a batch of 64, a hidden size of 8192, and 8 processors. The swap moves about 112 KB, against 512 KB for an All-Gather approach. Memory reads per processor drop from about 64 MB to about 8 MB. The claims also cover grouping GPUs into ranks and assigning query heads.

From the filing · THE ABSTRACT
… exchanges two or more of the attention values between the different processors, and computes an output of the transformer at different ones of the processors using different weight partitions of a Feed-forward Network (FFN).

Translation: Multiple chips share intermediate results and split up the final math.

Why faster chatbot replies start with chips

If you use a chatbot, the payoff is speed. The slow part of answering is often chips waiting on data, either from each other or from memory. Trimming the data they swap, and reloading less of the model per chip, targets exactly that wait. The filing says the approach suits small to medium conversation lengths, meaning hundreds to thousands of tokens (word pieces).

For Nvidia, this is software-and-hardware know-how that makes its chips look better at serving AI models. The filing says it is not tied to one product: it lists GPUs, CPUs, data centers and many other processor types as places the method could run. Anyone running a large chatbot service cares about response time, so even modest gains in how chips divide the work could matter at that scale.

Nvidia's 62nd filing we've tracked since July in our AI chip wars watch builds on spreading memory across chips and regrouping chips mid-reply.

Editorial take

You will never see this feature. What you might notice is a chatbot that answers a little faster when many people are using it at once. That is the whole benefit, and it depends on whether a company running a service adopts the method.

The numbers in the filing are small, tidy examples (112 KB versus 512 KB), so they show the idea works on paper but say little about a real data center. A 78% cut in swapped data sounds large, yet the filing does not say how much faster a full answer arrives.

The claims are broad, covering any processor group that splits requests, swaps attention results and then splits the second stage. For readers, that makes this a routine plumbing improvement with a clear and modest payoff: quicker replies, with no new feature to try.

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The drawings

26 drawing sheets from US 2026/0350352 A1 · click any drawing to enlarge

Dividing a stream of user questions across multiple AI chips, drawing sheet 1 from US 2026/0350352 A1
Sheet 1 Dividing a stream of user questions across multiple AI chips
Two traditional ways chips split up language model calculations, drawing sheet 2 from US 2026/0350352 A1
Sheet 2 Two traditional ways chips split up language model calculations
Dividing your question across four chips at once, drawing sheet 3 from US 2026/0350352 A1
Sheet 3 Dividing your question across four chips at once
How chips swap intermediate answers before generating the next word, drawing sheet 4 from US 2026/0350352 A1
Sheet 4 How chips swap intermediate answers before generating the next word
Steps for sharing text tasks among chips without memory bottlenecks, drawing sheet 5 from US 2026/0350352 A1
Sheet 5 Steps for sharing text tasks among chips without memory bottlenecks
A data center rack that powers AI models, drawing sheet 6 from US 2026/0350352 A1
Sheet 6 A data center rack that powers AI models
An all-in-one chip that packs computing cores and memory together, drawing sheet 7 from US 2026/0350352 A1
Sheet 7 An all-in-one chip that packs computing cores and memory together
Specialized graphics chip parts that handle massive parallel math tasks, drawing sheet 8 from US 2026/0350352 A1
Sheet 8 Specialized graphics chip parts that handle massive parallel math tasks
Show the other 18 sheets
Graphics chip parts that process visuals in parallel, drawing sheet 9 from US 2026/0350352 A1
Sheet 9 Graphics chip parts that process visuals in parallel
A hybrid chip combining regular computing with AI, drawing sheet 10 from US 2026/0350352 A1
Sheet 10 A hybrid chip combining regular computing with AI
Inside a multi-core server chip built to execute complex programs, drawing sheet 11 from US 2026/0350352 A1
Sheet 11 Inside a multi-core server chip built to execute complex programs
Specialized accelerator hardware designed to handle heavy AI computations, drawing sheet 12 from US 2026/0350352 A1
Sheet 12 Specialized accelerator hardware designed to handle heavy AI computations
Brain-inspired silicon cores connected together to process information, drawing sheet 13 from US 2026/0350352 A1
Sheet 13 Brain-inspired silicon cores connected together to process information
Connected server racks sharing heavy computing jobs, drawing sheet 14 from US 2026/0350352 A1
Sheet 14 Connected server racks sharing heavy computing jobs
Compute engines grouped inside an advanced multi-die accelerator chip, drawing sheet 15 from US 2026/0350352 A1
Sheet 15 Compute engines grouped inside an advanced multi-die accelerator chip
Central computing dies tied together across high-speed connections, drawing sheet 16 from US 2026/0350352 A1
Sheet 16 Central computing dies tied together across high-speed connections
Inside a chip core that runs chatbot tasks, drawing sheet 17 from US 2026/0350352 A1
Sheet 17 Inside a chip core that runs chatbot tasks
Math circuits and memory paired to speed up AI, drawing sheet 18 from US 2026/0350352 A1
Sheet 18 Math circuits and memory paired to speed up AI
Components inside an open design computing core, drawing sheet 19 from US 2026/0350352 A1
Sheet 19 Components inside an open design computing core
Grids of networked miniature processors built to handle AI text, drawing sheet 20 from US 2026/0350352 A1
Sheet 20 Grids of networked miniature processors built to handle AI text
Software layers that connect everyday apps to underlying chips, drawing sheet 21 from US 2026/0350352 A1
Sheet 21 Software layers that connect everyday apps to underlying chips
How software splits work between computers and AI chips, drawing sheet 22 from US 2026/0350352 A1
Sheet 22 How software splits work between computers and AI chips
Translating Nvidia code to run across competing graphics cards, drawing sheet 23 from US 2026/0350352 A1
Sheet 23 Translating Nvidia code to run across competing graphics cards
Self driving car computers linking navigation cameras, radar, and steering, drawing sheet 24 from US 2026/0350352 A1
Sheet 24 Self driving car computers linking navigation cameras, radar, and steering
Hardware setups that run AI calculations inside chips, drawing sheet 25 from US 2026/0350352 A1
Sheet 25 Hardware setups that run AI calculations inside chips
Teaching an AI model before using it on new questions, drawing sheet 26 from US 2026/0350352 A1
Sheet 26 Teaching an AI model before using it on new questions
Browse all the drawings 26 drawing sheets
Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.
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