Intel · Filed Dec 29, 2025 · Published Jul 16, 2026 · verified — real USPTO data

New Patent Speeds Up How Graphics Cards Draw Images on Screen

Every frame your GPU draws gets chopped into small zones called tiles, and Intel is filing a patent for a smarter way to organize those zones into groups before the drawing even starts.

Intel Patent: Hierarchical Tiling for Graphics Rendering — figure from US 2026/0203990 A1
Figure from the official USPTO publication.
Publication number US 2026/0203990 A1
Applicant Intel Corporation
Filing date Dec 29, 2025
Publication date Jul 16, 2026
Inventors Subramaniam Maiyuran, Jorge F. Garcia Pabon, Raghavendra Kamath Miyar, Sudheendra Srivathsa, Krishan Malik, Narsim Krishna, Rajalakshmi Athimoolam, Amit Mishra
CPC classification 345/422
Grant likelihood Medium
Examiner CENTRAL, DOCKET (Art Unit OPAP)
Status Docketed New Case - Ready for Examination (Apr 10, 2026)
Parent application is a Continuation of 17128708 (filed 2020-12-21)
Document 20 claims

How Intel's two-level screen-splitting speeds up drawing

Imagine a painter working on a giant mural. Instead of zigzagging all over the canvas, they section it off into large blocks, then smaller squares inside each block, and work area by area. That's roughly what Intel is proposing for graphics processors.

When your computer draws a scene on screen, the GPU splits the image into small patches called tiles and figures out which objects land in which patch. Intel's patent adds a layer on top of that: it groups tiles into super tiles, so the chip can sort through a whole batch of objects at once and figure out which large zones they touch before bothering with the finer details.

The result is that the GPU does less redundant work. Instead of checking every tiny tile against every object in the scene, it narrows things down in two steps, large zone first, small tile second. That kind of efficiency matters most in scenes with lots of overlapping shapes, where the old approach wastes time on tiles that turn out to be empty.

How super tiles batch and replay object intersections

The patent describes a hardware unit that handles tile-based rendering (a technique where the screen is divided into small rectangular zones and each zone is processed independently, which saves memory bandwidth compared to drawing the whole image at once).

What Intel adds is a hierarchical (two-level) organization on top of that:

  • Batch formation: incoming objects are grouped into batches before any tile work begins.
  • Super tile fill sequencing: the hardware identifies which large "super tile" zones each batch of objects overlaps, rather than immediately checking every small tile.
  • Tile fill intersects: once the relevant super tiles are known, the hardware zooms in and computes exactly which small tiles inside each super tile are actually touched by each object.
  • Replay sequencing: the hardware can replay the sequence of objects for each super tile, meaning it processes geometry in an order that keeps related data together.

The key insight is that by working in two passes (coarse zone, then fine tile), the chip avoids testing every object against every tiny tile. That's especially valuable in complex scenes where most objects only cover a small fraction of the screen.

What this means for Intel's GPU rendering pipeline

Tile-based rendering is already the dominant approach in mobile GPUs (Qualcomm, Apple, ARM) because it cuts memory traffic. Intel is pushing that architecture further with this hierarchical grouping layer, which suggests the company is working to make its integrated and discrete graphics hardware more competitive on power-efficient rendering workloads.

For everyday users, better tiling logic can mean games and graphics apps draw frames faster without the GPU working as hard. It also fits into a broader trend of GPU makers borrowing ideas from mobile chip design to cut power use on laptops and handhelds, where battery life and heat matter as much as raw performance.

Editorial take

This is a fairly deep internal engineering patent, the kind that rarely makes headlines but does real work inside a GPU. Intel's integrated graphics have long lagged Apple Silicon's tile-based efficiency, and this filing suggests the company is taking that gap seriously at the architecture level. Worth a look if you follow GPU design, not especially relevant to anyone else.

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Source. Full patent text and figures from the official USPTO publication PDF.

Editorial commentary on a publicly published patent application. Not legal advice.