Nvidia · Filed Mar 21, 2025 · Published Sep 24, 2026 · verified — real USPTO data

Nvidia Patents a Way to Keep Graphics Data on the Right Chip

When a graphics card is actually two chips sharing the work, getting them to stop passing data back and forth constantly is harder than it sounds. Nvidia has a plan for that.

Two graphics processing units (uGPU1 and uGPU2) on an interposer, connected to memory and a central processing unit. Drawing from patent filing US 2026/0289721 A1.
Two graphics processing units (uGPU1 and uGPU2) on an interposer, connected to memory and a central processing unit.
See all 34 drawings from this filing ↓
Publication number US 2026/0289721 A1
Applicant NVIDIA Corporation
Filing date Mar 21, 2025
Publication date Sep 24, 2026
Inventors Ziyad HAKURA, Yan ZHANG, Eric LUM, Andrei KHODAKOVSKY, Eric WERNESS, Emmett KILGARIFF, Wishwesh Gandhi, Michael Fetterman
CPC classification 382/305
Grant likelihood Medium
Examiner SHIMELES, BEZAWIT NOLAWI (Art Unit 2673)
Status Docketed New Case - Ready for Examination (May 13, 2025)
Document 35 claims

What Nvidia's render-target routing actually does for you

Ever had your computer stutter mid-game because something behind the scenes couldn't keep up? In high-end graphics cards built from two chips side by side, one big cause of that stutter is data taking a detour to the wrong chip.

Nvidia's patent describes a system where each chip "owns" a specific portion of the screen. When your GPU is drawing pixels on the left side of your display, the first chip handles those pixels using its own nearby memory. Pixels on the right go to the second chip and its memory. No long trips across the connection between chips.

The result is that the image data being written during rendering stays local, meaning each chip does its work without constantly asking the other for help. Less back-and-forth between chips means faster rendering and fewer of those frustrating hitches.

From the filing · CLAIM 1
selecting one of the first processor or the second processor to execute one or more threads associated with one or more pixels, wherein the selecting is based on screen location coordinates of the one or more pixels and a mapping …

Translation: The system decides which chip handles a pixel based on where it appears on the screen.

How Nvidia maps screen pixels to local chip memory

The patent describes a render target localization system for GPUs built from multiple chips (called dies) on a single card. "Render target" is GPU-speak for the temporary image buffer where a chip writes pixel data before it gets sent to your screen.

Here is how the system works at a high level:

  • Screen region mapping: The system splits the screen into regions and assigns each region to a specific chip and its attached memory. A pixel at screen coordinate (x, y) is routed to the chip that "owns" that part of the screen.
  • Local memory writes: Once a chip is assigned a pixel, it stores all the color, depth, and shading data for that pixel in its own local memory, rather than writing to shared or remote memory across the chip interconnect.
  • Virtual memory interleaving: Under the hood, the chips share a single virtual address space (meaning software sees one continuous block of memory), but the physical data lands on whichever chip's memory is locally attached. This keeps compatibility with existing rendering code.
  • Mixed bit-density surfaces: The patent specifically addresses storing surfaces of different data sizes (for example, a 32-bit color buffer alongside an 8-bit stencil buffer) on the same local memory and accessing them consistently, which is a practical engineering challenge in this setup.

The core goal is cutting inter-chip traffic (data that has to travel across the physical link between the two dies), which is the main bottleneck in multi-chip GPU designs.

From the filing · THE ABSTRACT
… localizing render targets in a multi-chip graphics processing unit (GPU) thereby reducing the inter-chip traffic and improving the latency of certain rendering …

Translation: Keeping graphics work on the same chip stops chips from slowing each other down by constantly sharing data.

What this means for high-end GPU performance

For most people, this kind of patent lives deep inside hardware they never see. But the payoff is concrete: games and professional 3D applications running on multi-chip GPUs spend less time waiting for data to arrive from the wrong chip. That translates to more consistent frame rates and fewer micro-stutters, the kind of brief freezes that are especially noticeable in fast-moving scenes.

Nvidia's interest in multi-chip GPU architecture shows up repeatedly in its filings, and this patent addresses one of the trickier plumbing problems in that space. As Nvidia pushes chip designs that link multiple dies together, keeping memory traffic local becomes a real engineering priority, not just a theoretical one.

Nvidia's 34th filing we've tracked since July in the GPU rendering race builds on earlier work like one that grows small textures and one that spots visual glitches.

Editorial take

That brief stutter when a complex scene loads in a demanding game is sometimes one processor waiting on data sitting in another processor's memory. This patent addresses exactly that delay by keeping the right data close to the chip that needs it, so the wait shrinks or disappears.

The approach works without asking game developers to change anything. The hardware figures out the routing on its own, which means players benefit automatically rather than waiting years for studios to rework their code.

For anyone who games on a high-end system, this shows up as smoother frame delivery in heavy scenes, not as a feature on the box. It is quiet, invisible engineering that prevents a failure most players could feel but never name.

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The drawings

34 drawing sheets from US 2026/0289721 A1 · click any drawing to enlarge

Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.
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