Samsung Display Patents a Dual Flip-Flop Timing Circuit for Display Gate Drivers

By Patentlyze Team · Updated Jul 10, 2026

Deep inside every display panel is a circuit that tells each row of pixels when to turn on. Samsung Display has filed a patent for a specific two-stage timing design meant to make that process more reliable.

What Samsung's gate driver timing fix actually does

Imagine a display screen as a grid of tiny lights. To show a picture, the display has to switch on each row of those lights in rapid sequence, thousands of times per second. The circuit responsible for triggering each row in the right order is called a gate driver, and getting its timing exactly right is essential for a clean, flicker-free image.

Samsung Display's patent covers a specific design for the building blocks inside that gate driver. Each block uses two separate timing circuits (called flip-flops) that work in alternation: one samples a signal on the way up of a clock pulse, and the other samples on the way up of an inverted version of the same pulse. Together, they pass a "carry" signal down the chain, like a relay baton, telling each row of pixels when its turn is.

The idea is to create a cleaner, more predictable handoff between each stage of the gate driver chain, which in theory reduces timing errors that could cause display artifacts.

How the two flip-flops hand off clock signals

The patent describes the internal architecture of a gate driver, the circuit that sequentially activates each horizontal row of pixels on a display panel so that image data can be written to them one line at a time.

Each stage in the gate driver chain contains a gate signal generator built around two flip-flops (basic digital memory elements that capture a signal at a precise moment in time) and an inverter:

• First flip-flop: Receives a clock signal and captures (samples) the carry output from the previous stage at the clock's rising edge, producing a "logic signal."
• Inverter: Takes that same clock signal and flips it, creating an inverted clock whose rising edge falls exactly between the original clock's pulses.
• Second flip-flop: Samples the logic signal at the rising edge of the inverted clock, producing the carry signal that gets passed to the next stage.

By splitting the carry propagation across two clock phases (the normal clock and its inverse), the design effectively doubles the timing resolution available for each handoff. The gate signal sent to the display panel's pixel rows is derived from the logic signal output, not the carry, keeping the two functions cleanly separated.

What this means for display panel manufacturing

For display panel engineers, gate driver reliability is a constant concern. Timing glitches in the gate driver chain can produce visible horizontal lines, flickering, or uneven brightness across the screen. A two-phase flip-flop design like this one can reduce those glitches by giving each stage a more stable signal to work with.

For ordinary consumers, the impact, if any, would be invisible by design: a display that works correctly. This is the kind of incremental circuit-level improvement that accumulates across panel generations. It's unlikely to be a feature Samsung markets by name, but patents like this are the building blocks that separate one manufacturer's panel quality from another's over time.

Editorial commentary on a publicly published patent application. Not legal advice.