Intel · Filed Mar 27, 2025 · Published Aug 6, 2026 · verified — real USPTO data

Intel Patents a Chip Security System That Quarantines Suspicious Messages Mid-Transfer

When a secure message between two chips just... never arrives, is that a glitch or an attack? Intel's new patent describes a chip that automatically assumes the worst and acts on it.

Intel Patent: Blocking Suspicious Tags in Secure Chip Channels — figure from US 2026/0228328 A1
Figure from the official USPTO publication.
See all 17 drawings from this filing ↓
Publication number US 2026/0228328 A1
Applicant Intel Corporation
Filing date Mar 27, 2025
Publication date Aug 6, 2026
Inventors Shalini Sharma, Christopher Van Beek, Filip Schmole, Arie Aharon, Raghunandan Makaram, Tessil Thomas
CPC classification 726/26
Grant likelihood Medium
Examiner GELAGAY, SHEWAYE (Art Unit 2436)
Status Prosecution Suspended/Delayed (May 21, 2025)
Parent application Claims priority from a provisional application 63754471 (filed 2025-02-05)
Document 20 claims

How Intel's tag-blocking system guards secure chip channels

Imagine you send a package and the delivery service says it's been picked up, but it never shows up at the destination. You'd probably want to put that tracking number on a watch list until you figured out what happened. That's essentially what this Intel patent does, but for data moving between chips inside a computer.

Modern servers use a security system called a Trusted Execution Environment (TEE) to handle sensitive tasks, like processing encrypted data in the cloud. Data sent between chips in this environment gets a unique label, called a tag, so the receiving side knows which request each response belongs to. If a response never comes back, Intel's invention says: quarantine that tag immediately. Don't let anything reuse it until the system figures out whether the silence was caused by a hardware glitch or an attacker trying to intercept or manipulate the data.

The patent also describes a way for security managers built into the chip to actively flush a secure communication channel, like clearing a clogged pipe, rather than waiting for things to sort themselves out.

How the IC spots a timed-out tag and locks it out

The patent describes a circuit block that sits inside an integrated circuit (the kind of chip that manages data routing in a server) and monitors a type of protected link called an IDE channel (Integrity and Data Encryption). IDE channels are part of the PCIe standard, which is the connection fabric that links a CPU to GPUs, network cards, storage drives, and other hardware inside a server.

Each request sent over an IDE channel carries a tag, a short numeric label that lets the receiving chip match responses to the right requests. If a response (called a completion message) doesn't arrive within a set time window, the circuit's detector fires an alert. An evaluation unit then identifies which tag was attached to the timed-out request and adds it to a prevented tag list, essentially a blocklist that stops any new request from reusing that tag.

The tag stays blocked until the system determines whether the timeout was innocent (a slow device, a congested link) or caused by a malicious actor trying to intercept or replay traffic. The patent also introduces a complementary mechanism:

  • A TEE Security Manager (TSM) or a Device Security Manager (DSM) can issue an explicit command to flush the entire IDE channel, forcing all in-flight data to be cleared out rather than potentially exploited.
  • The root complex (the main hub chip that connects the CPU to all other devices) or any attached IO device can trigger these protections.
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What this means for server and cloud hardware security

Server chips handling confidential workloads, think cloud VMs processing health records or financial data, depend on the IDE channel staying trustworthy. A classic attack called a replay attack involves an adversary capturing a valid message and re-sending it later to trick the system. By quarantining a tag the moment its expected response goes missing, Intel's approach closes a window that attackers could use to sneak a replayed or forged response in under a legitimate tag number.

For data center buyers and cloud providers, this is the kind of low-level plumbing that makes confidential computing promises actually hold up. It also aligns with Intel's TDX (Trust Domain Extensions) platform, which already relies on hardware-enforced isolation. A more defensive IDE layer strengthens the whole stack without requiring software changes from cloud tenants.

Editorial take

This is deep chip infrastructure work, not a flashy consumer feature, but it addresses a real and underappreciated attack surface in confidential computing. The tag-blocklist idea is straightforward and practical, and the addition of an explicit channel-flush command shows Intel is thinking about recovery, not just detection. Worth attention from anyone following cloud security hardware.

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The drawings

17 drawing sheets from US 2026/0228328 A1 · click any drawing to enlarge

Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.

Editorial commentary on a publicly published patent application. Not legal advice.