Intel Patents a Chip That Decides How Much AI Thinking to Skip
Intel has filed a patent for hardware that, before running an AI calculation, quickly estimates whether taking a shortcut would actually be faster than doing the full calculation, and then picks the winning option on the fly.
What Intel's attention-pruning chip actually does
An AI model stares at a massive grid of numbers, every single one potentially important. You pay for all of that processing whether it matters or not.
Intel's patent describes a chip that pauses before each big calculation and runs a quick timing test. It asks: would it be faster to first strip this grid down to only its most important values, then do the calculation on the smaller version? Or is the full grid actually quicker to process as-is? Whichever path wins the estimate, that is the path the chip takes.
The idea is that the right answer changes depending on the size of the data and the state of the hardware at that moment. Instead of forcing engineers to hard-code one strategy, the chip adapts on every pass, potentially saving time without sacrificing the quality of the AI's output.
… estimate first execution time of selecting a number k of dominant data elements from the initial self-attention input matrix to generate a sparse self-attention input matrix …
Translation: The chip calculates how long it will take to filter out the less important data to speed up processing.
How the chip times three paths before picking one
Transformer models, the architecture behind large language models and many image-recognition systems, rely on a step called self-attention. Self-attention is the process by which the model figures out which parts of the input are most relevant to each other. It is computationally expensive because it involves multiplying large matrices (grids of numbers) together.
One common optimization is sparse attention: instead of using the full matrix, you pre-select only the k most important values (called dominant elements) and throw the rest away before doing the big multiplication. The catch is that the selection step itself costs time, and on some inputs or hardware states, that overhead makes the sparse path slower than just running the full calculation.
Intel's patent describes processor circuitry that estimates three time costs before committing:
- First execution time: how long it would take to find and extract the top-k dominant elements from the full input matrix.
- Second execution time: how long the self-attention calculation would take using that smaller, sparse matrix.
- Third execution time: how long the self-attention calculation would take using the original, full matrix with no pruning at all.
The chip adds the first and second estimates together (sparse path total) and compares that sum to the third estimate (full path). It then executes whichever path is projected to be faster. Because this decision happens at runtime on actual hardware, it can respond to real conditions rather than relying on a fixed policy baked in at design time.
… estimating third execution time of performing the self-attention operation based on the initial self-attention input matrix …
Translation: It also measures the time required to process all the data without skipping any steps.
What this means for AI chips running transformer models
AI inference (running a trained model to get an answer, as opposed to training it) is where most of the real-world compute cost lives. Every millisecond shaved from an inference pass multiplies across millions of requests. A chip that dynamically chooses between full and sparse attention could improve throughput without requiring software developers to tune workload-specific settings for each deployment.
For teams building AI accelerators or evaluating Intel's next-generation silicon, this filing signals Intel is working on hardware-level adaptivity rather than leaving optimization entirely to software libraries. The broader pattern of chip makers embedding decision logic directly into silicon is one area where plain-English patent summaries of Intel's AI chip filings are giving engineers and analysts an early read on where processor design is heading.
Intel's 27th filing we've tracked since May in our AI chip wars watchlist adds to one splitting AI work across chips and one splitting model memory at runtime.
The patent claim covers any chip or processor that calculates exactly three time estimates and then acts on those comparisons. That is a clean description, but it also means the whole claim stands or falls on that specific three-estimate setup. Any rival design that uses two estimates, or four, or merges two into one, probably falls outside the protection entirely.
So the patent guards a specific decision structure, not the broader idea of skipping unnecessary calculations to save time. That narrow scope limits how much it can threaten competitors. It also makes Intel's claim easier to defend in court, because what Intel built matches the claim precisely.
There are more where this came from
We read every patent application Big Tech publishes and send you the ones worth knowing. Plain English, free, every week.
The drawings
9 drawing sheets from US 2026/0244906 A1 · click any drawing to enlarge
Want this weekly breakdown for a company we don't cover? Patentlyze Pro →