AMD · Filed Dec 23, 2024 · Published Jun 25, 2026 · verified — real USPTO data

AMD Patents Software That Teaches Computers to Run Programs in Smarter Order

Every time your computer runs a program, a compiler has to decide the exact order in which thousands of tiny instructions get executed. AMD thinks a neural network can do that job better than the hand-written rules engineers use today.

AMD Patent: Neural Network-Based Instruction Scheduling — figure from US 2026/0178338 A1
FIG. 1A — rendered from the official USPTO publication PDF.
Publication number US 2026/0178338 A1
Applicant Advanced Micro Devices, Inc.
Filing date Dec 23, 2024
Publication date Jun 25, 2026
Inventors Ian Charles Colbert, Jake Matthew Daly
CPC classification 717/140
Grant likelihood Medium
Examiner CENTRAL, DOCKET (Art Unit OPAP)
Status Docketed New Case - Ready for Examination (Jan 30, 2025)
Document 20 claims

What AMD's AI instruction scheduler actually does

Imagine a kitchen with one chef and a hundred tasks: chop onions, boil water, preheat the oven. The order matters. Starting the oven first means it's ready when you need it. A bad order wastes time even if every individual task gets done. Your processor faces the same problem, at billions of operations per second.

Right now, the software tool that compiles your code (turning human-readable programs into processor instructions) uses fixed rules to decide that order. AMD's patent describes replacing those static rules with a neural network that learns which ordering of instructions tends to run fastest.

The system reads a program's instructions, converts them into numerical representations an AI can process, and then picks instructions one at a time, each time predicting which choice will lead to the best overall performance. The result is a ranked list of possible instruction orderings, and the best one gets handed off to the processor.

How the neural network scores and picks each instruction

The patent describes a neural instruction scheduler that sits inside a compiler, the tool that translates source code into machine instructions before a program runs.

Here's the pipeline the patent lays out:

  • The compiler maps a program's logic into a directed acyclic graph (DAG), a flowchart-like structure where each node is an instruction and edges show which instructions depend on which others.
  • Each instruction node gets converted into numerical tokens, which retrieve embeddings (compact numerical descriptions that capture what an instruction does and how it relates to others) from a learned lookup table.
  • Those embeddings are combined into a single vector representing the current state of the schedule, then fed into a value estimator, a neural network trained to predict how much each candidate next-instruction will help overall performance.
  • The scheduler picks the top-scoring instruction, adds it to the schedule, and repeats the process for every remaining instruction, a technique called autoregressive generation (the same step-by-step approach language models use to write text, one token at a time).

The output is one or more candidate instruction schedules, ordered sequences the processor can execute. The compiler then selects the best one.

What this means for compiler performance on AMD chips

Instruction scheduling is one of those compiler problems that has been solved with hand-tuned heuristics for decades. Those rules work reasonably well, but they can't adapt to the specific mix of instructions a particular program generates. A learned scheduler could, in principle, find orderings that keep AMD's execution units busier and reduce stalls, translating to faster software without any changes to the source code.

For AMD, this matters most in high-throughput workloads like AI inference, graphics, and scientific computing, exactly the markets where the company competes most aggressively. If this approach makes it into AMD's compiler toolchain (like ROCm or LLVM back-ends), developers would get a performance boost automatically when they recompile.

Editorial take

This is a genuinely interesting bet on replacing one of the oldest and most stable parts of the compiler stack with a learned model. The autoregressive framing is clever, borrowing a proven approach from language models and applying it to a very different domain. Whether it clears the bar of being faster and reliable enough to ship in a production compiler is the real question, but it's the kind of research-to-toolchain pipeline AMD needs to close the software gap with Nvidia.

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Source. Full patent text and figures from the official USPTO publication PDF.

Editorial commentary on a publicly published patent application. Not legal advice.