Samsung Patents a Chip That Handles Two Data Tasks Simultaneously
Most processor cores finish one memory task before starting the next. Samsung is patenting a design that lets a chip run a read-modify-write operation and an unrelated memory instruction at the same time, cutting the waiting around.
What Samsung's parallel memory operation chip actually does
Imagine you're at a diner and the cook can only flip one pancake at a time. Every time a new order comes in, it sits on the counter until the current pancake is done. That's roughly how many processor cores handle memory tasks today.
Samsung's patent describes a chip design that adds a dedicated helper circuit for a specific, common type of memory operation called read-modify-write (when a chip reads a value, changes it, and writes it back). While that helper is busy with its job, the main memory unit doesn't just sit idle. It picks up the next memory task in line, as long as that task isn't waiting on the first one to finish.
The result is that two memory-related jobs happen in overlapping clock ticks instead of one after the other. That kind of parallel execution is a standard way chip designers squeeze more performance out of the same hardware without raising the clock speed.
How the RMW circuit and LSU share clock cycles
The patent describes a processor core built around two cooperating memory circuits. The first is a standard load-store unit (LSU), which handles everyday read-and-write instructions: move data from memory into a register (a tiny on-chip storage slot), or push data from a register back to memory. The second is a new dedicated read-modify-write (RMW) circuit.
A read-modify-write instruction bundles three steps into one: load a value, compute something with it (add 1, flip a bit, etc.), then write the result back. These are extremely common in loops and data-processing routines.
The key innovation is in how the instruction decoder (the part of the chip that figures out what to do next) coordinates the two circuits:
- In clock cycle 1, it hands the load portion of an RMW instruction to the RMW circuit.
- Also in clock cycle 1, it scans ahead for the next memory instruction that has no dependency on the RMW operation (meaning it doesn't need the result of that operation to proceed).
- In clock cycle 2, the LSU processes that independent instruction while the RMW circuit continues its compute-and-store steps.
By overlapping these two streams, the core avoids the stall that would normally occur while waiting for the RMW instruction to fully complete.
What this means for Samsung's chip performance ambitions
For Samsung, this is chip-design housekeeping at the microarchitecture level, the kind of incremental improvement that accumulates into real performance gains across millions of instructions per second. It doesn't require a new manufacturing process or bigger transistors; it's a smarter way to schedule the work already happening inside the core.
Samsung designs processors for its own mobile devices (the Exynos line) and sells chips to other manufacturers. A more efficient memory pipeline directly improves performance-per-watt, which matters enormously in phones and other battery-powered devices. Whether this ends up in a future Exynos core or in a specialized AI or embedded processor is an open question, but the underlying technique is broadly applicable to any chip doing repetitive data-processing work.
This is exactly the kind of unglamorous but genuinely useful chip engineering that separates competitive processor teams from the rest. It won't show up in a product announcement, but optimizing how a core handles overlapping memory operations is real work that accumulates into better benchmark numbers and lower power draw. Worth noting, but not worth losing sleep over unless you follow Samsung's semiconductor roadmap closely.
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The drawings
8 drawing sheets from US 2026/0228007 A1 · click any drawing to enlarge
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Editorial commentary on a publicly published patent application. Not legal advice.