Nvidia · Filed Mar 9, 2026 · Published Sep 10, 2026

Nvidia Patents a Method to Run AI Processing Steps on Separate Chips

Every AI model you interact with runs a long chain of calculations, one layer feeding the next. Nvidia's new patent describes a way to run those layers on separate chips at the same time, cutting the wait.

A neural network is trained with data and then processed by two separate GPUs. Drawing from patent filing US 2026/0268651 A1.
A neural network is trained with data and then processed by two separate GPUs.
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Publication number US 2026/0268651 A1 US20260268651A1
Applicant NVIDIA Corporation
Filing date Mar 9, 2026
Publication date Sep 10, 2026
Inventors Wentao Zhu, Daguang Xu, Can Zhao, Ziyue Xu, Holger Reinhard Roth
US classification 706/25
Status when we published Waiting for an examiner (Jun 5, 2026)
Parent application is a Continuation of 16885170 (filed 2020-05-27)
Document 21 claims

How Nvidia's layer-splitting idea speeds up AI responses

Every time you ask an AI chatbot a question or use a photo app that recognizes faces, a chain of math happens inside the computer. Each step in that chain has to finish before the next one can start, which means the whole process is only as fast as its slowest step.

Nvidia's patent describes a system that watches how each step in that chain depends on the others, then ships the results of one step directly to a second chip so the next steps can start running in parallel. Instead of a single chip working through the whole chain by itself, the work gets spread out.

The goal is to cut the time it takes an AI to produce an answer, which engineers call inference time. Faster inference means snappier AI features in apps, faster image recognition in cameras, and quicker responses from AI assistants.

From the filing · THE ABSTRACT
… copying output from one layer of the neural network to another computing resource based on dependencies among layers in the network …

Translation: Moving data between different computer chips depending on what the neural network needs next.

How output gets copied between chips and layers

At its core, the patent covers a processor that analyzes the dependency graph of a neural network (a map of which layers need results from which other layers) and then routes the output of one layer to a separate computing resource so that two or more downstream layers can start processing immediately.

The key mechanism is output copying. When layer A finishes its calculation, the result is copied to another chip or compute unit without waiting for the entire network to run sequentially. Because the system knows in advance which later layers don't depend on each other, it can run them in parallel on those separate resources.

In practical terms, the patent describes:

  • A processor with one or more circuits that orchestrates this split
  • Mapping of layer dependencies so the system knows what can be parallelized
  • Routing of intermediate outputs to the correct compute resource at the right time

This is essentially a pipeline parallelism strategy (breaking a sequential process into overlapping stages, the way an assembly line works) applied to neural network inference, not just training.

What faster AI inference means for real products

Inference speed is one of the biggest cost and experience factors in modern AI. Every millisecond shaved off a model's response time reduces compute costs for companies running AI at scale, and makes AI features feel instant rather than sluggish to end users. Nvidia's steady investment in inference optimization reflects how competitive this space has become.

For you as a consumer, faster inference translates directly into AI assistants that respond without a noticeable pause, real-time video effects that don't drop frames, and medical imaging tools that flag results in seconds rather than minutes. The underlying technique here isn't tied to one product category, so its impact, if widely deployed, would touch any device or service running a neural network.

This is the 44th Nvidia filing we've tracked in our AI training and infrastructure coverage since May, alongside earlier applications like multiplying robot training videos and splitting AI workloads across machines.

Editorial take

The first independent claim in this patent was canceled before publication, leaving nothing enforceable on the page. A patent lives or dies by its claims, and with claim 1 gone, there is no legal boundary defining what Nvidia would own or what a hardware maker would need to work around.

What the abstract describes is a real engineering idea: finish one stage of AI processing, copy the result to a separate chip, and let the next stages run simultaneously rather than waiting in line. That kind of parallel handoff can meaningfully cut the delay between a user asking a question and an AI system answering it.

Whether this filing ever gains a surviving claim that locks down a specific version of that idea is still unresolved. Until it does, the document describes a promising technique without protecting one.

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The drawings

57 drawing sheets from US 2026/0268651 A1 · click any drawing to enlarge

Neural network training and processing., drawing sheet 1 from US 2026/0268651 A1
Sheet 1 Neural network training and processing.
Encoder-decoder processing on devices., drawing sheet 2 from US 2026/0268651 A1
Sheet 2 Encoder-decoder processing on devices.
Parallel processing throughput comparison., drawing sheet 3 from US 2026/0268651 A1
Sheet 3 Parallel processing throughput comparison.
Steps for pipeline parallelism training., drawing sheet 4 from US 2026/0268651 A1
Sheet 4 Steps for pipeline parallelism training.
Steps for modifying neural networks., drawing sheet 5 from US 2026/0268651 A1
Sheet 5 Steps for modifying neural networks.
Accuracy and inference speed on HAN., drawing sheet 6 from US 2026/0268651 A1
Sheet 6 Accuracy and inference speed on HAN.
Accuracy and inference speed on liver., drawing sheet 7 from US 2026/0268651 A1
Sheet 7 Accuracy and inference speed on liver.
Training hardware structure components., drawing sheet 8 from US 2026/0268651 A1
Sheet 8 Training hardware structure components.
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Browse all the drawings 57 drawing sheets
Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.
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