On Tuesday OpenAI posted a photo of Jalapeño, the inference chip it designed with Broadcom, and said the test results show “more intelligence from every watt and faster responses.” Two hours later Sam Altman put it in six words: “we made a chip and it is fast.” The same day, OpenAI’s head of hardware, Richard Ho, stood up at the Hot Chips conference at Stanford and gave the first detailed look at the chip. The numbers OpenAI put on the slide: 1.5 to 1.9 times more work per watt than what it runs today, and 1.7 to 3.6 times lower latency on the models it tested.
Back in June we wrote that OpenAI had started patenting chips, and that the next filing would tell us whether the custom silicon program was real and iterating. Since then five more chip filings have published, OpenAI has shown the chip, and Ho’s own name turns out to be on the earliest one. Here are all seven, and what each one has to do with the chip OpenAI is now showing off. You do not need an engineering background for any of this. Every filing below links to our full breakdown, where we translate the patent into plain English: what it does, why it matters, and what we make of it. If you can follow a recipe, you can follow these.
One caution before we start, because it matters. A patent describes an idea a company wants to own. It does not describe a product. None of these filings mentions Jalapeño, and OpenAI has not said which of them made it into silicon. What we can do is put the filings next to what OpenAI disclosed on Tuesday and see where they line up.
The filing with the chip designer’s name on it
The oldest of the seven is the one to read first. Filed on December 6, 2024 and published this June, it covers a chip that stacks memory directly on top of the processor. The four inventors are Clive Chan, Ravi Narayanaswami, Kaushik Vaidyanathan, and Chian-min Richard Ho. That is the same Richard Ho who presented Jalapeño on Tuesday.
The filing is about one specific job. When a language model writes a reply, it keeps a running record of everything in the conversation so far, called the key-value cache. Every new word the model produces requires a lookup against that record. The lookup is not hard math. The expensive part is hauling the record back and forth between memory and the circuits doing the comparison.
OpenAI’s answer in the filing is to stop hauling. Stack the memory in layers, put the processor underneath, and connect them with vertical wires so short that the patent puts a number on it: under 2 millimeters in the main claim, and as little as 0.05 millimeters in the description. Some of the comparison math can even happen inside the memory layers themselves.
Now look at how OpenAI described Jalapeño on Tuesday. Per The Register’s writeup, each chip carries 216 GB of HBM4 memory in six stacks, moving 15.4 terabytes per second, and the guiding idea is that “model state, including the KV cache used while generating a response, can be explicitly placed and kept local.” The KV cache is the exact workload the December 2024 filing names. Stacked memory connected by vertical wires is exactly what HBM is.
There is a real difference, and we would rather say it than have you find it. The patent puts the memory stacks on top of the processor die. On Jalapeño, the HBM4 stacks sit beside the compute die on the same package, which is the standard way to use HBM today. Same goal, shorter wires and a KV cache that never travels far, but not the same packaging. Read the filing as the problem statement Ho’s team started from, not a blueprint of the finished chip.
Do the math where the data lives
The next two filings attack the same cost from a different direction. Instead of moving the memory closer to the math, they move the math into the memory.
A tiled chip architecture, filed January 23, 2026, describes a grid of small self-contained tiles. Each tile stores a block of the model’s weights, the numbers learned during training, and multiplies incoming data against them right where they sit. A small general-purpose processor next to each tile handles the odd jobs the multiply circuits cannot, and a converter between tiles translates number formats on the fly so one tile can run at lower precision than its neighbor.
A second filing, from March 23, 2026, covers running matrix math forward and backward on the same stored weights. Normally a chip needs a second, flipped copy of a weight matrix to run the transposed version of a calculation. This design keeps one copy in place and changes the wiring that reads it.
The common thread is a pattern chip designers call weight-stationary: the weights stay put, the inputs stream past them. According to SemiAnalysis’s breakdown of the Hot Chips talk, Jalapeño’s main engine is a weight-stationary systolic array, the same broad family as Google’s TPU. Ho led TPU work at Google before OpenAI hired him in late 2023, and Narayanaswami is a co-author of Google’s original TPU paper. The filings and the chip agree on the philosophy even where the circuits differ.
Four-bit math without the rounding errors
Jalapeño gets its headline number, 13.4 petaflops per chip, by doing most of its math in a four-bit format called MXFP4. Four-bit numbers are tiny. The trick that makes them usable is to store one shared scale factor for each small block of numbers, so the block as a whole can represent a wider range than any single four-bit value could. That block-scaling idea is what the “MX” in the name refers to.
Two filings published on August 20, both filed February 17, 2026, are about exactly this kind of arithmetic. One covers a compute engine that switches between decimal-style and whole-number math on demand, picks a precision, and cuts power to whatever part of the circuit the current mode does not need. The other covers a version of the same engine built to live inside a memory block, with a normalization step that runs at a slightly wider precision so results do not get rounded off badly.
The line to underline in the second filing is that the engine “applies block-level scaling with dequantization.” Block-level scaling is the MX idea in patent language. A chip that runs MXFP4 has to do this somewhere. These two filings describe a circuit that does it.
Both were filed three months after Jalapeño’s reported tape-out, the point where a design is frozen and sent to the factory, so the specific circuits here may be for the next chip rather than this one. OpenAI called Jalapeño generation one of a multi-generation roadmap on Tuesday. This is what generation two’s arithmetic could look like.
Skipping the multiplications that are always zero
The third August 20 filing is the one that speaks most directly to Altman’s “fast” and to OpenAI’s per-watt claims. It covers hardware that skips calculations it knows will be zero.
A large share of the numbers inside a trained model are zero, and multiplying anything by zero gives you zero. Most chips do that multiplication anyway. This design watches the incoming numbers, flags a zero before the multiply happens, writes a zero straight to the output, and switches off the idle multiplier. Because the weights stay loaded in place, the chip can decide once per weight which multipliers to darken and leave them dark for the whole batch.
The filing says weight-stationary in as many words. It is the clearest example of the seven filings and the Hot Chips slides describing the same machine from two sides. Whether the B0 silicon OpenAI benchmarked actually skips zeros this way, OpenAI has not said.
Search inside the memory
The seventh filing is the outlier, and the one with the most obvious product attached. Also filed February 17, it covers similarity search that runs inside the memory chip. When ChatGPT searches a document store to answer a question, it compares the question’s numerical fingerprint against millions of stored fingerprints, and today that means pulling all of them out of memory to check. This design does the comparison where the fingerprints are stored and sends back only the matches.
That is retrieval, not the core language model, so it is a step removed from Jalapeño. It tells you the hardware team’s scope is wider than one accelerator.
The seven filings, in order
- Stacked memory on the processor. Filed December 6, 2024. Inventors include Richard Ho. Target: the KV cache.
- Tiled compute-in-memory architecture. Filed January 23, 2026.
- Mixed floating-point and integer engine. Filed February 17, 2026.
- The same engine, inside a memory block. Filed February 17, 2026.
- Zero-skipping multipliers. Filed February 17, 2026.
- Similarity search inside memory. Filed February 17, 2026.
- Transposed matrix math on stationary weights. Filed March 23, 2026.
Six of the seven carry the name Mohammed Fouda, an OpenAI hardware engineer. Ho’s filing is the one that predates everything else by more than a year, and it sits inside the sixteen-month window that reportedly ran from hiring the team to tape-out.
What these filings do and don’t prove
All seven are published applications, not granted patents. Our breakdowns are written for readers, not lawyers, and the original filings are linked from each one if you want the source. The USPTO has not examined any of them yet, and the claims can narrow a lot before grant. Anyone can check their status through the USPTO’s public search, which is where we read them.
They also do not tell you what is on the Jalapeño die. Six of the seven were filed after the chip reportedly taped out in November 2025, so they describe work that came after this design was frozen. And a patent’s job is to stake out territory, so some of these will describe ideas OpenAI wants to own rather than ideas it has built.
What they do show is a hardware group that has been filing steadily for twenty months on one theme: stop moving data. Shorter wires to the KV cache. Math inside the memory. Weights that never leave their cells. Multipliers that switch off when the answer is already known. Every one of the performance claims OpenAI made on Tuesday, more work per watt and lower latency, comes down to that theme. The filings are where you can watch the team work it out.
There is one more piece of OpenAI’s chip portfolio the filings do not cover. Earlier this month The Information reported that OpenAI bought patents from Rain AI, the chip startup Altman had backed, after passing on buying the company. Those will show up under Rain’s name at the patent office, not OpenAI’s, so they are outside this list.
What to watch next
OpenAI says Jalapeño ships in small volumes by the end of this year and ramps through 2027. The filings that describe generation two will start publishing about eighteen months after they are filed, which means the next wave lands through 2027 as well. The things we will be reading for: a filing that names a Broadcom co-inventor, a filing that moves the KV cache work from stacked memory to the on-chip cache, and anything that mentions the four-bit block format by name.
We track every OpenAI chip filing as it publishes. Follow along on our OpenAI patents hub and on the AI chip wars watchlist, where these seven sit alongside what Nvidia, Google, Amazon, and Apple are filing against them. For everything else Big Tech filed this week, start at the Patentlyze front page. If you are new to reading patents, start with our guide to how Big Tech patents work.
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