OpenAI Patents a Circuit That Runs Calculations Faster by Switching Math Types Automatically
OpenAI has filed a patent for a compute engine that can flip between two different styles of math on demand, and powers down the parts it isn't using to save energy. It's a chip-level design that could make AI inference cheaper and more predictable.
What OpenAI's switchable number-format chip actually does
Imagine a car with both a gas engine and an electric motor, where the car automatically switches between them depending on what the road demands. OpenAI's patent describes something similar inside a chip: a compute engine that can handle two different styles of math, switching between them as needed.
Most AI work uses floating-point numbers (think: very precise decimals) because they can represent a huge range of values. But some tasks, especially after a model is trained, work just fine with simpler integers (whole numbers), which are faster and cheaper to calculate. This engine handles both, using the same core hardware, and shuts off the parts it isn't using so they don't waste power.
When the chip knows it only needs lower precision, it also adjusts how much of its memory and calculation circuitry is active. That keeps energy use in check and makes timing more predictable, which matters a lot when you're running thousands of operations per second inside a data center.
… gate portions of the compute engine responsive to the selection; and the compute engine comprises: operand registers for operand values; compute circuitry configured, in the floating-point mode, to produce a mantissa product and a product exponent and to combine signs; …
Translation: Shutting down unused parts of the processor saves energy and keeps speeds steady.
How the shared selection network handles both math modes
The compute engine at the center of this patent performs vector-matrix multiplication, the core math operation behind nearly every AI model. What makes it unusual is that the same physical hardware can operate in two distinct modes, selected by a controlling processor.
- Floating-point mode: Numbers are split into a sign, an exponent, and a mantissa (the decimal part). The engine computes the mantissa product and the exponent separately, then uses a circuit called a power-of-two generator to shift (align) the result into the right position before adding everything up.
- Integer mode: The same alignment circuit, called a selection network, is repurposed to handle bitwise integer multiplication. Negative numbers are managed using two's-complement correction (a standard technique for storing negative integers in binary) before accumulation.
- Gating: Whichever mode is inactive, those datapath sections are electrically disabled, reducing power draw and stabilizing timing.
Results from many parallel calculations flow through adder trees (think: a tournament bracket that progressively sums numbers) and then into a hierarchical accumulator sized to the chosen precision. A normalization stage then rounds and formats the final number.
The system also supports optional dequantization, which folds scaling factors into the exponent calculation. This is important for quantized AI models, where numbers are compressed for efficiency and need to be rescaled before use. The design works both in conventional accelerators and in compute-in-memory chips, where the math happens inside the memory array itself rather than shipping data to a separate processor.
… normalization performs leading-one detection, mode-dependent exponent correction, rounding, and zero flushing.
Translation: The chip cleans up the math results by rounding numbers and wiping away zeroes.
What this means for the cost of running AI calculations
For anyone running AI workloads at scale, the cost of computation is largely a function of power consumption and hardware utilization. A chip that can run demanding training-style math when needed, then drop into a lower-power integer mode for inference, without swapping out hardware, is genuinely useful at the data-center level. The power gating means idle circuitry isn't burning energy, and predictable latency matters for time-sensitive serving pipelines.
The compute-in-memory support is also worth noting. Moving data between memory and processors is one of the biggest energy costs in modern AI hardware. Doing the math inside the memory array directly attacks that problem. OpenAI is a software company that has been investing heavily in custom hardware, and filings like this one show up regularly in the plain-English patent summaries that track where AI chip design is heading.
OpenAI's second chip application we've tracked since July in the AI chip wars watchlist follows their forward-and-backward chip filing with another look at custom silicon.
The design saves hardware by making one circuit do two jobs. But that creates a problem: the chip controlling everything must predict which job is coming next, or there is a penalty for switching late. Get the prediction wrong and the slowdown ripples through every step that follows.
That gamble pays off when the workload is predictable and planned in advance. For anyone building new software on top of this chip, though, there is simply more that can go wrong.
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The drawings
8 drawing sheets from US 2026/0244404 A1 · click any drawing to enlarge
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