Intel Patents a Chip That Hides Its Own Secret-Scrambling Work from Attackers

By Patentlyze Team · Updated Jul 10, 2026

Most security chips protect the data going in and out, but Intel's new patent focuses on something sneakier: hiding what the chip is doing on the inside, so an attacker watching its power draw or timing can't reconstruct the secret key.

What Intel's masked cryptography chip actually does

Imagine someone can't read your safe's combination, but they can watch how long it takes you to open it, and they can measure the electricity it draws. Given enough observations, a careful attacker could work backwards and guess the combination. That's roughly how a "side-channel attack" works against security chips.

Intel's patent describes a chip designed to defeat that kind of attack. The key idea is masking: every sensitive value inside the chip gets combined with a random number before any real computation happens. From the outside, the power consumption and timing look like random noise because the chip is, in a sense, always working on scrambled data.

The tricky part, which this patent specifically addresses, is converting between different number formats inside the chip without accidentally leaking the secret through that conversion step. Intel's design bakes those conversions directly into the arithmetic circuits, so there's no exposed moment where the real value briefly appears in the clear.

How the masking, conversion, and adder circuits work together

The patent describes a hardware block built to run HMAC-SHA-2 (Hash-based Message Authentication Code using the SHA-2 family of hash functions, a standard way to verify that a message hasn't been tampered with) in a way that resists side-channel attacks.

The core technique is Boolean masking: state values inside the chip are XOR'd with random numbers generated by a permuted congruential generator (a fast, low-cost random number source built directly on the chip). Attackers watching power or electromagnetic emissions see only the masked values, not the real ones.

The three main engineering contributions are:

• Multiplexer-based masked logic: The non-linear operations SHA-2 requires (called Choose and Majority functions) are implemented using simple selector circuits that stay in the masked domain without extra conversion steps.
• Integrated BtoA conversion inside the adder: Converting between Boolean masking and arithmetic masking (two different ways of hiding a number) is normally a vulnerable step. This design folds that conversion directly into a carry-save-adder, eliminating the exposure window.
• Sparse-tree arithmetic-to-Boolean converter: When the chip needs to strip off the arithmetic mask at the end of a computation, it uses a compact tree-based adder structure that does so without revealing the unmasked value to any observable signal.

Taken together, these three pieces form a complete, area-efficient pipeline that keeps every intermediate value masked from input to output.

Why side-channel attacks make this kind of chip necessary

Side-channel attacks are a real and documented threat to cryptographic hardware, used in practice against smart cards, security tokens, and embedded processors. As Intel pushes into data-center security chips, confidential computing, and hardware security modules, having a provably masked HMAC accelerator matters for certifications like FIPS 140-3 and for customer trust in sensitive workloads.

For you as an end user, this kind of chip work is largely invisible until it isn't. The benefit shows up when your bank's HSM, your laptop's security enclave, or a cloud server's trusted execution environment resists an attack that would otherwise expose signing keys or authentication secrets. Getting the masking right at the silicon level is the kind of foundational work that keeps those systems trustworthy.

Editorial commentary on a publicly published patent application. Not legal advice.