Intel Patents a Chip Shortcut That Spends Video Quality Where Viewers Look
Intel's patent teaches a video chip to spend more detail on faces and less on empty walls, without asking software to redo the math for every tiny square of every frame.
What Intel's region-based video patent does
A video call shows you sitting in front of a plain wall. Your face matters. The wall does not. Video compression already exploits this by spending fewer bits on the boring parts so the stream stays smooth.
The trouble is the bookkeeping. Today, software often has to work out how hard to squeeze every small square of every frame, over and over, which costs time and power. Intel's patent hands that arithmetic to the video chip itself.
The app simply says a bit more detail here, a bit less there for each square. The chip combines those nudges with its own overall quality setting and finishes the job, with limits so the result never drifts out of range.
combine respective ones of the delta quantization parameters with a reference quantization parameter to determine a plurality of adjusted quantization parameters corresponding respectively to the plurality of pixel blocks …
Translation: The system tweaks quality settings for individual blocks of pixels by merging local adjustments with a baseline number.
How the chip adds, then clamps, each block
Video compression chops each frame into small tiles called pixel blocks. Each tile gets a number called the quantization parameter, or QP (a dial for how hard to squeeze that tile: a low QP keeps more detail, a high QP squeezes harder and saves data).
Two things set that dial. Rate control software tied to the chip picks a frame-level QP, a single baseline chosen to hit a target data rate. The app, such as a game stream or video conferencing tool, supplies a delta QP map: a grid with one signed adjustment per block. In the filing's example, a baseline of 30 plus a delta of -8 in the center gives 22 (more detail), while a delta of 11 near the edge gives 41 (more compression).
The encoder hardware then does the sum for every block, with a safety limit:
- Add the delta to the frame-level QP.
- If the sum is above the upper limit, use the upper limit.
- If it is below the lower limit, use the lower limit.
- Otherwise, use the sum.
The description's example range runs from 10 to 51.
Before, the app supplied absolute values, and software had to recompute a final QP for every block of every frame whenever the baseline changed. Here the app does not need to know the baseline at all. The filing says moving the sum onto the chip removes that software overhead and saves power.
… receiving, at the hardware encoder, from an application, a delta quantization parameter map, the delta quantization parameter map comprising per-pixel block quantization parameter modifications for respective pixel blocks of the first video frame …
Translation: Software feeds a special map into the hardware to tell it how much quality each specific part of the image needs.
Why this matters for streams and video calls
If you watch a game stream, join video calls, or rely on security cameras, you are the target audience. The filing names all three as places where it pays to give important areas more detail and static areas less. Doing the per-block math in hardware could mean the same picture quality for less processor work and less power, which matters most on laptops and busy servers.
For Intel, this is plumbing in the graphics hardware that sits underneath many video apps. App makers get a simpler job: they describe which regions matter, and the chip handles the rest. Nothing here promises a visible leap in picture quality. The gain is efficiency, and it shows up as smoother streams and longer battery life.
Intel's 21st filing we've tracked since May in the GPU rendering race builds on ideas like their memory tile fetch work and their AI frame fill work.
Claim 21 is short and broad. It needs a processor to produce a per-block adjustment, plus encoder circuitry that adds each adjustment to a base quality number, keeps the answer inside a configurable range, and compresses the block. That is the whole recipe: addition, a floor and a ceiling, applied tile by tile.
The claim never names a video standard or a particular app, so if granted it would reach any chip that splits the work this way. The later claims add narrower details: signed adjustments on an unsigned base, a base number chosen to hit a target data rate, and the exact floor-and-ceiling logic.
The math itself is plain arithmetic, so the value rests on where it happens: inside the encoder circuitry instead of in software. For a chip maker, a small saving repeated on every block of every frame adds up, which makes a modest idea reasonable to protect.
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The drawings
5 drawing sheets from US 2026/0313122 A1 · click any drawing to enlarge
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