Microsoft · Filed Apr 25, 2025 · Published Oct 29, 2026

Microsoft's New Patent Removes the Central Traffic Bottleneck From AI Computing Hardware

Inside the racks that run AI, one big traffic-directing switch eats power and space. Microsoft's filing proposes wiring small switches into each tray ahead of time, so no software has to direct the traffic.

AI servers stacked together and wired directly to each other so computing jobs finish much faster without network traffic jams. Drawing from patent filing US 2026/0343778 A1.
AI servers stacked together and wired directly to each other so computing jobs finish much faster without network traffic jams.
See all 6 drawings from this filing ↓
Publication number US 2026/0343778 A1 US20260343778A1
Applicant Microsoft Technology Licensing, LLC
Filing date Apr 25, 2025
Publication date Oct 29, 2026
Inventors Nitin BHARDWAJ
US classification 710/317
Examiner YIMER, GETENTE A (Art Unit 2181)
Status when we published Waiting for an examiner (May 28, 2025)
Document 20 claims

What Microsoft's switch-free AI rack does

Imagine an office where every employee's mail has to pass through one central sorting room, run by a clerk following a rulebook. It works, but the room takes up space, burns electricity, and sometimes backs up.

That is roughly how the computers behind AI are wired today. A rack holds many specialized AI chips, and one large switch directs data between them. Microsoft's filing removes that big switch. Instead, small crossbar switches (grids of tiny links that connect inputs to outputs) sit inside each tray of chips. They are set up in advance for one specific AI model, so every incoming cable already has a fixed exit.

Because the routes never change, no software has to direct traffic. The filing says that saves power, frees rack space for more trays, and costs less than the big switch.

From the filing · CLAIM 1
… a y-dimension crossbar switch configured to a fixed AI model communication topology; an x-dimension crossbar switch configured to the fixed AI model communication topology; …

Translation: Two specific switches are hardwired to handle AI communication in a rigid pattern.

How the pre-wired crossbars link each chip

A rack is a tall cabinet of computers. Each tray in it holds a set of AI accelerators (specialized chips built for the math behind AI, such as tensor processing units). In a typical setup, cables from all those chips run to one network switch, which routes data under software control.

The filing puts two crossbar switches into every tray, one for the x direction and one for the y direction. Both are set to a fixed communication topology, meaning a routing plan worked out in advance for the specific AI model that will run. Each cable going in has one set exit, so nothing needs to decide anything while the model runs.

The claims give a concrete layout:

  • A tray holds sixteen chips in four groups of four.
  • Cables link groups side to side through one switch and top to bottom through the other.
  • Across a rack, a third switch joins the trays (four in one example), set to the same plan.

The switches can pass data forward or loop it back, and the description says every chip ends up within one crossbar hop (one jump through a switch) of its destination. The switches are Ethernet-based serializer/deserializer parts, which convert data between many-lanes-at-once and single-lane form for fast travel.

From the filing · THE ABSTRACT
… replace the network switch typically included in an AI accelerator rack with crossbar switches that are added to trays of AI accelerators within the rack.

Translation: Standard network switches are removed and replaced with direct crossbar switches on the hardware trays.

Why a smaller switch could cut AI server costs

If you use a chatbot or an image tool, the hardware behind each answer is expensive to build and to power. Data center power and rack space are a big part of that bill. The filing says pre-wired switches would use far less power than a software-controlled one, cost less, and free room in the rack, so the same cabinet could hold more trays and more computing.

Because the routes are fixed, a rack wired this way is built around one model's traffic plan. That suits large, steady jobs. The filing names no product, so treat it as a design direction for data centers, something behind the scenes that would only show up for you as cheaper or faster AI services.

That makes this Microsoft's 22nd filing we've tracked since July in the AI chip wars watchlist, adding to work like cheaper math for AI and lower memory for text generation.

Editorial take

Claim 1 is short. It covers a tray with several AI chips, two switches that are each set to a fixed, model-specific routing plan, and cables linking different sets of chips across them. It names no chip count and no chip type, so a tray of any size with that two-switch layout falls inside the wording as written.

The one firm requirement is the fixed plan. A tray whose switches are reconfigured by software as workloads change would sit outside that language. The later claims add detail: sixteen chips in four groups of four, Ethernet switches, and a third switch joining four trays.

If granted, it would cover a specific wiring layout, and a reasonably wide one at the tray level. As an engineering swap of one big switch for several small ones, it is a modest idea with a clear payoff in power and space.

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The drawings

6 drawing sheets from US 2026/0343778 A1 · click any drawing to enlarge

Existing AI chip trays rely on a central network switch, drawing sheet 1 from US 2026/0343778 A1
Sheet 1 Existing AI chip trays rely on a central network switch
Microsoft links AI chips directly using grid switches, drawing sheet 2 from US 2026/0343778 A1
Sheet 2 Microsoft links AI chips directly using grid switches
Stacking multiple chip trays into a deep computing rack, drawing sheet 3 from US 2026/0343778 A1
Sheet 3 Stacking multiple chip trays into a deep computing rack
Connecting separate trays across a third switching path, drawing sheet 4 from US 2026/0343778 A1
Sheet 4 Connecting separate trays across a third switching path
Steps for wiring AI chips across horizontal and vertical paths, drawing sheet 5 from US 2026/0343778 A1
Sheet 5 Steps for wiring AI chips across horizontal and vertical paths
Standard computer parts that manage the system hardware, drawing sheet 6 from US 2026/0343778 A1
Sheet 6 Standard computer parts that manage the system hardware
Browse all the drawings 6 drawing sheets
Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.
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