Microsoft Patents a Memory-Access Rule That Speeds Up Video Encoding Chips
Every time you stream a video or join a video call, a chip somewhere is frantically copying blocks of pixels around to compress the image. Microsoft has patented a rule that stops those chips from doing a particularly slow kind of memory lookup, and the fix is almost insultingly simple.
How Microsoft's encoding shortcut keeps chips from stalling
Ever tried to grab a file that's half on your desk and half in a storage closet down the hall? That split-fetch is exactly what video encoding chips run into millions of times per second, and it costs time.
When a video encoder compresses an image, it looks for patches of the current frame that already appeared nearby, then records just the difference rather than copying the whole thing. This technique, called intra block copy, is great for efficiency. But when the patch it wants to reuse sits right on the boundary between two memory zones (one fast, one slow), the chip has to reach into both at once, which slows everything down.
Microsoft's patent fixes this by drawing a hard line. A reference patch must live entirely inside one memory zone or the other. Straddling the boundary is simply not allowed. The encoder finds the next-best patch that fits cleanly in one place, saves the memory headache, and moves on. It sounds like a small rule, but at the speed chips run, avoiding millions of split fetches adds up fast.
… prohibits the reference block from being at a third location at which the reference block overlaps both the current CTU and the previous CTU …
Translation: The system forbids the computer from looking at data that straddles the boundary between two different memory areas.
How the block vector constraint splits on-chip and off-chip memory
The patent covers intra block copy (IBC) prediction, a compression technique used in video and image codecs (think of a codec as the software or hardware recipe for squishing video into a smaller file). IBC works by finding a rectangular patch of pixels somewhere earlier in the same frame, then saying "use that" instead of storing the pixels fresh. The encoder records only a block vector (BV), a two-number address describing where the reusable patch lives.
The problem this patent solves is a hardware memory mismatch. In a real chip, fast on-chip memory (small, expensive, built right into the processor) holds one region of the frame, while slower off-chip memory (external RAM, farther away) holds a larger surrounding region. If the reference patch straddles the boundary between these two regions, the chip must coordinate two separate memory reads simultaneously, which is slow and complex to implement.
Microsoft's solution is a location constraint: the reference block must sit entirely inside the on-chip region (the current coding tree unit, or CTU, which is just a fixed-size tile of the frame) or entirely inside the off-chip region (the previous CTU to the left). Any patch that would overlap both regions is simply ruled out during encoding. The encoder picks the best legal patch instead.
- If the best patch is fully inside the current CTU, one fast on-chip read fetches it.
- If it's fully inside the previous CTU, one off-chip read fetches it.
- A patch crossing the boundary is forbidden, so split reads never happen.
The claim also requires that the patch contain only pixels already reconstructed (decoded so far), which is a standard codec rule to keep encoding and decoding in sync.
… an encoder/decoder can avoid memory access operations that are split between on-chip memory and off-chip memory when retrieving the sample values of the reference block.
Translation: This rule prevents the chip from having to fetch data from two different types of memory at the same time.
What this means for video hardware at the chip level
For anyone designing video encoding hardware (the chips inside cameras, streaming boxes, video-conferencing gear, or phones), split memory reads are a real engineering headache. They require extra buffering logic, add cycles to every affected operation, and can create timing problems that force designers to slow the chip down or add silicon area. A simple rule baked into the codec standard sidesteps all of that without changing the core compression algorithm.
Microsoft has been active in the video codec space for years, and this filing fits a pattern of making codecs more hardware-friendly rather than just chasing better compression ratios. The constraint is narrow enough (one CTU boundary, one memory split) that it won't upset the broader codec ecosystem, but broad enough that any encoder implementing IBC prediction for that boundary case would need to work around it. Compression-focused new Big Tech patents on video encoding chip design have been picking up and this one shows how a single memory-access rule can ripple out into licensing conversations across the hardware industry.
Microsoft's 11th filing we've tracked in our AI chip wars watchlist since July follows earlier applications like one blocking cross-chip data fetches and one using light as a processor.
Claim 1 is specific but meaningful in scope. It covers any computer-readable media that enforces this exact boundary rule during IBC encoding: no reference block may straddle the line between the current CTU and the previous CTU. That is narrow enough to be defensible, but IBC is a standard feature in codecs like VVC and HEVC, so any hardware encoder implementing IBC near CTU boundaries would land squarely inside this claim if granted.
The practical consequence is straightforward: a competitor building a video encoding chip that wants to avoid split memory reads would need to either license this rule or engineer around it (perhaps by choosing a different memory partition scheme, which carries its own costs). The claim does not require the on-chip/off-chip memory split to exist physically; it requires only that the software enforce the location constraint. That wording is broad.
As an editorial verdict: this is a solid, defensible filing with real engineering motivation behind it. It is not a patent on a grand idea; it is a patent on a specific, implementable fix to a specific hardware problem. Those tend to hold up better in disputes than sweeping conceptual claims, which makes this one more commercially useful than it looks at first glance.
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The drawings
14 drawing sheets from US 2026/0254974 A1 · click any drawing to enlarge
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