Intel Patents a Chip-Level Defense Against Memory Spying Between Programs
Two programs running on the same chip can spy on each other through the processor's own cache memory, without touching each other's files at all. Intel's new patent describes hardware that blocks this class of attack at the chip level, before software ever gets a chance to help.
How Intel stops programs from peeking at each other's data
You're renting space on a cloud server, and so is a company you've never heard of. Your code and theirs run on the same physical chip, sharing the same fast memory buffer called a cache. A clever attacker can watch how long it takes your code to load data from that cache and, from those timing differences alone, piece together what the other program is doing or storing. That attack technique is called a side-channel attack, and it's a known, real threat in shared computing environments.
What Intel is patenting here is a hardware fix baked into the chip itself. The idea is straightforward: if a program (technically called a "security domain") requests a piece of shared data from the cache, the chip checks whether that program has ever loaded that exact data before. If the answer is no, the chip pretends the data isn't there and fetches a fresh copy from main memory instead. The attacker's timing trick stops working because every domain always sees the same fetch time, regardless of what anyone else has loaded.
This matters most on cloud infrastructure, where dozens of customers' workloads run side by side on the same hardware. Intel is trying to make those shared environments safer at a layer that software patches can't easily reach.
… implement the side-channel protection for the data, including to not provide a cache line corresponding to the memory address from the cache to the first security domain, when the cache line exists in the cache and is valid, if the first security domain has not previously accessed the cache line in the cache.
Translation: The chip blocks a program from reading shared memory if it has not accessed that specific data before.
How the cache withholds lines from uninitiated security domains
The patent centers on a modified cache controller, the circuitry inside a processor that manages what data lives in the fast on-chip cache and who can read it.
Normally, when any program asks for a piece of data, the cache checks whether that data is already stored (a "cache hit"). If it is, the chip returns it immediately. That speed difference between a hit and a miss is precisely what side-channel attacks exploit: a timing spy can tell whether another program recently loaded the same data, leaking information about what that program is doing.
Intel's patent changes the rule for shared data (data that multiple security domains are allowed to read) when side-channel protection is active. The steps work like this:
- A security domain (think: one customer's virtual machine or one isolated process) requests a shared memory address.
- The cache controller checks a separate record of which domains have already loaded that specific cache line.
- If the requesting domain has never loaded it before, the controller treats it as a miss, even if the data is sitting right there in cache. It fetches a fresh copy from slower main memory.
- On future requests, the domain is now on the "has accessed this" list and gets normal fast-path responses.
The net effect is that an attacker watching timing signals sees a consistent pattern: first access always takes full memory-fetch time, regardless of what other domains have done. The information leak through timing is eliminated for that access pattern.
The circuitry is to receive a memory access request for data at a memory address from a first security domain. The data at the memory address is to be shared by a plurality of security domains including the first security domain. A side-channel protection is to be used for the data.
Translation: The system identifies when multiple programs are trying to use the same piece of memory and applies security rules.
What this means for cloud servers and shared-chip security
Cloud computing runs on shared hardware, and the security gap Intel is targeting here is not theoretical. Spectre and Meltdown, the processor vulnerabilities disclosed in 2018, showed the world that cache timing attacks can extract passwords, encryption keys, and other secrets from programs that are supposed to be completely isolated from each other. Operating system patches and software mitigations helped, but they carry performance penalties and don't cover every scenario. A hardware-level fix that operates below the software stack is a cleaner answer.
The tradeoff is real: forcing a full memory fetch on first access adds latency, and on workloads that constantly share fresh data across security domains, that penalty could stack up. Intel is betting that the security guarantee is worth the occasional slowdown, which is a reasonable call for the data-center customers most exposed to this threat. Processor-level security has been one of the more active areas among interesting tech patents since the Spectre era, and Intel's approach here shows the work is still far from finished.
That makes this Intel's 30th filing we've tracked since May in the AI chip wars, adding to work like the mid-instruction memory bookmark and the thread-collision GPU fix.
Intel's design makes a deliberate choice to ignore a perfectly good answer sitting in memory, which sounds wasteful because it is. When two separate customers' software shares data on the same server, the processor pretends it doesn't already have that data ready, forcing a slower retrieval the first time each customer asks for it. That front-loaded slowdown is the price of closing a timing-based eavesdropping hole.
The trade reads as reasonable for long-running server workloads that quickly build up a history of what they've accessed. The penalty fades fast once that history exists.
The design shows strain against short-lived cloud functions that spin up, run one small task, and shut down before any history accumulates. Those jobs would pay the full penalty on nearly every single request, which could make a security feature feel more like a performance tax on exactly the lightweight work modern cloud infrastructure depends on most.
There are more where this came from
We read every patent application Big Tech publishes and send you the ones worth knowing. Plain English, free, every week.
The drawings
21 drawing sheets from US 2026/0252498 A1 · click any drawing to enlarge
Want this weekly breakdown for a company we don't cover? Patentlyze Pro →