Samsung · Filed May 18, 2026 · Published Sep 17, 2026

Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks

Every time your phone's memory chip is busy working through a command, the controller talking to it is still running at full speed, burning power for no reason. Samsung's new patent describes a fix: drop the clock speed when memory is busy, and ramp it back up the moment it's ready.

A memory controller and a memory device are connected, with the controller managing clock signals and data transfer. Drawing from patent filing US 2026/0279420 A1.
A memory controller and a memory device are connected, with the controller managing clock signals and data transfer.
See all 21 drawings from this filing ↓
Publication number US 2026/0279420 A1 US20260279420A1
Applicant Samsung Electronics Co., Ltd.
Filing date May 18, 2026
Publication date Sep 17, 2026
Inventors Hyungjin Kim, Jungsik Park, Soongmann Shin
US classification 365/233.1
Status when we published Waiting for an examiner (Jun 11, 2026)
Parent application is a Continuation of 18806359 (filed 2024-08-15)
Document 21 claims

How Samsung's clock-switching memory idea saves power

Imagine your phone's processor is like a manager who keeps checking in on an employee every second, even when that employee is clearly head-down in a long task and won't be ready to report back for a while. All that checking-in burns energy for nothing.

Samsung's patent tackles exactly that scenario inside your device's memory system. When your phone sends a command to its memory chip, that chip raises a little flag that says "I'm busy." Under this design, the memory controller sees that flag and dials its own internal clock speed down to a lower, power-sipping rate. It's not doing anything useful at full speed anyway.

The moment the memory chip finishes and drops that busy flag, the controller ramps the clock back up to full speed so it's ready to send the next command without delay. The whole handoff is automatic, with no manual tuning required.

How the controller reads busy signals to shift clock speed

The patent centers on a memory controller, the chip that acts as the go-between for a processor and the actual memory storage. When the controller sends a command to the memory device, it watches for a status signal (in many memory standards, called a Ready/Busy pin) that the memory chip drives high to say "I'm occupied."

On seeing that signal asserted (set active), the controller switches its own clock to a lower frequency. Because clock speed is one of the biggest drivers of power consumption in digital chips, running at a lower frequency directly reduces how much energy the controller burns during the waiting period.

When the memory device finishes its internal operation and de-asserts the status signal (returns it to the ready state), the controller automatically switches back to the higher clock frequency. The design handles this through a clock-switching circuit that can change frequencies in response to the status signal, without needing the main processor to intervene.

The patent covers the controller itself, the memory device that drives the status signal, the combination of the two as a system, and the method as a process that any compatible hardware could implement.

What lower memory power draw means for phones and servers

For smartphones and tablets, memory system power is one of the less obvious drains on battery life. A controller that runs at full clock speed even while waiting on slow memory operations is wasting energy on idle cycles. A design that cuts that waste automatically, across every busy-wait period, could add up to meaningful real-world battery savings without any change to how apps behave.

For servers and storage systems, where thousands of memory operations happen per second, the power savings per chip are small, but the aggregate across a data center rack matters. This is a low-drama, infrastructure-level improvement: not a feature you'd ever see advertised, but exactly the kind of efficiency gain that compounds across every device that ships with it.

Samsung's 51st filing we've tracked in the AI chip wars since June follows work like dedicated AI data storage and a two-stage sentence-skipping reader.

Editorial take

The core idea here is straightforward: when a memory chip is busy doing its own work, the controlling processor dials down its clock speed, then ramps back up when the memory is ready again. That signal about whether memory is busy or ready already exists in common memory standards, so nothing new has to be invented or manufactured to make this work.

The shortest path to a shipping product is a design update, not a factory change. No new materials, no new fabrication process, just a circuit that watches an existing signal and adjusts a clock accordingly. That is about as close to ready as a patent idea gets.

The document does not quantify how much power this actually saves, which is the honest remaining question. But the mechanism itself is simple enough that it could appear inside a future chip without requiring any announcement at all.

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The drawings

21 drawing sheets from US 2026/0279420 A1 · click any drawing to enlarge

Memory controller and memory device, drawing sheet 1 from US 2026/0279420 A1
Sheet 1 Memory controller and memory device
Memory device internal components, drawing sheet 2 from US 2026/0279420 A1
Sheet 2 Memory device internal components
3D NAND flash memory block, drawing sheet 3 from US 2026/0279420 A1
Sheet 3 3D NAND flash memory block
Cross-section of memory device, drawing sheet 4 from US 2026/0279420 A1
Sheet 4 Cross-section of memory device
Read operation flowchart, drawing sheet 5 from US 2026/0279420 A1
Sheet 5 Read operation flowchart
Read operation timing diagram, drawing sheet 6 from US 2026/0279420 A1
Sheet 6 Read operation timing diagram
Read operation signal flow, drawing sheet 7 from US 2026/0279420 A1
Sheet 7 Read operation signal flow
Write operation flowchart, drawing sheet 8 from US 2026/0279420 A1
Sheet 8 Write operation flowchart
Show the other 13 sheets
Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 9
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 10
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 11
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 12
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 13
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 14
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 15
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 16
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 17
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 18
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 19
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 20
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Samsung Patents a Chip That Cuts Power Use by Slowing Down During Idle Memory Tasks patent drawing, sheet 21
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Browse all the drawings 21 drawing sheets
Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.
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