Samsung · Filed Jan 12, 2026 · Published Oct 22, 2026

Samsung Files Patent for Memory Chips That Do Some of an AI's Math Themselves

Your AI chatbot spends a lot of its time waiting for data to arrive from memory. Samsung's filing puts calculators inside and beside the memory so the lightest steps never have to travel.

A memory chip connects to a central computer chip and does some of the math on its own to speed up heavy AI tasks. Drawing from patent filing US 2026/0330207 A1.
A memory chip connects to a central computer chip and does some of the math on its own to speed up heavy AI tasks.
See all 23 drawings from this filing ↓
Publication number US 2026/0330207 A1 US20260330207A1
Applicant Samsung Electronics Co., Ltd.
Filing date Jan 12, 2026
Publication date Oct 22, 2026
Inventors Yongsuk Kwon, Sangsu Park, Jung Ho Ahn, Juhwan Cho, Kwanhee Kyung, Jinin So, Sungmin Yun
US classification 706/15
Status when we published Waiting for an examiner (Mar 9, 2026)
Document 20 claims

What Samsung's three-tier memory chip actually does

Ever watched a cook sprint to the pantry for every ingredient, carry it back to the stove, then repeat? That back-and-forth wastes more time than the cooking itself. Computers running AI chatbots have the same problem: the chip doing the math spends a lot of its time waiting for data to arrive from memory.

Samsung's filing tries to fix that by letting the memory do some of the work. It describes a memory device with three places where math can happen: the main processor (the chip that usually runs AI), a helper unit sitting next to the memory, and tiny calculators built right inside the memory chips. Each step of an AI model goes to whichever place fits it best.

The most math-heavy steps stay with the main processor. Medium steps go to the helper unit. The light steps that mostly just read lots of data are handled inside the memory itself, so that data never has to travel at all.

From the filing · CLAIM 1
A heterogeneous computing memory device comprising: a memory including a processing-in-memory (PIM) unit; a processing-near-memory (PNM) unit; and a controller configured to receive first to third requests from an external processing device …

Translation: The chip combines standard storage with built-in processors to handle tasks right where the data lives.

How each AI layer gets routed to its best worker

The core is a memory device with a controller (the traffic manager) that takes requests from an outside processor over a host channel (the link to the main chip). Each request names one layer of an AI model, and each layer has a computational intensity: how many math operations it needs per byte of data it reads.

  • Highest intensity: the controller reads the stored data and sends it out to the main processor, which does the math.
  • Middle intensity: the controller tells a processing-near-memory unit (a helper chip beside the memory) to pull data over the memory channel and process it.
  • Lowest intensity: the memory does the work itself using processing-in-memory circuits (small calculators built into the memory chips), so the data never leaves.

The description walks through chatbot-style language models. One common form of the attention step (multi-head attention) is low intensity and runs inside the memory. Two other forms (grouped-query attention and mixture-of-experts feed-forward layers) land in the middle tier. Claim 9 covers that split.

The filing also describes extras: the main processor can work on one piece while memory finishes another, the link can use the CXL standard (a fast connection for pools of memory), and the parts can be stacked in one package.

From the filing · THE ABSTRACT
… controls the PNM unit to process the second layer in response to the second request, and controls the memory to process the third layer in response to the third request.

Translation: The system routes different parts of an AI workload to different processing units based on how complex the math is.

Why AI memory bottlenecks matter for data centers

If this works, you would feel it indirectly: AI chatbots that answer faster and cost less to run in data centers. A big limit on chatbot speed is how quickly data moves from memory to the processor, and the processor often sits idle waiting. Doing the lightest steps inside the memory cuts that traffic, and the middle steps get their own helper instead of crowding the main chip.

Samsung makes memory, so a design that makes memory do more of the work fits naturally with what it sells. The filing covers several physical forms, from memory modules to stacked chips in one package to data-center servers, so it is meant to fit many setups. It gives no speed or energy numbers, so the size of the gain stays unknown.

Samsung's 62nd filing we've tracked since June in our AI chip competition work, it builds on one keeping chatbots quick and one cutting chip idle time.

Editorial take

Claim 1 covers a memory device that bundles three things at once: calculators inside the memory, a helper unit beside it, and a controller that sends heavy, medium and light layers of work to the right place. Leave out any one of those and the claim no longer fits, so a design with only two tiers falls outside it.

The wording is wide in other ways. Claim 1 says 'layer' and never names a chatbot, and it sets no number for what counts as heavy, medium or light. Only claim 9 narrows things down to language models.

If granted, it would cover any memory device that divides AI work this three-way. The filing gives no speed or energy figures, so the payoff is unproven. The split itself is simple to picture and would be easy to spot in a finished product.

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The drawings

23 drawing sheets from US 2026/0330207 A1 · click any drawing to enlarge

Combining normal computer memory with two built-in calculation units, drawing sheet 1 from US 2026/0330207 A1
Sheet 1 Combining normal computer memory with two built-in calculation units
Adding miniature computing cores inside individual memory storage banks, drawing sheet 2 from US 2026/0330207 A1
Sheet 2 Adding miniature computing cores inside individual memory storage banks
How computers split up an AI task, drawing sheet 3 from US 2026/0330207 A1
Sheet 3 How computers split up an AI task
Sending heavy calculations back to the main processor to finish, drawing sheet 4 from US 2026/0330207 A1
Sheet 4 Sending heavy calculations back to the main processor to finish
Pulling stored data to the main chip, drawing sheet 5 from US 2026/0330207 A1
Sheet 5 Pulling stored data to the main chip
Letting storage chips calculate light AI tasks on their own, drawing sheet 6 from US 2026/0330207 A1
Sheet 6 Letting storage chips calculate light AI tasks on their own
Returning completed math directly from the storage chip, drawing sheet 7 from US 2026/0330207 A1
Sheet 7 Returning completed math directly from the storage chip
Routing medium-difficulty math to an on-board companion processor, drawing sheet 8 from US 2026/0330207 A1
Sheet 8 Routing medium-difficulty math to an on-board companion processor
Show the other 15 sheets
Routing medium workload math through an off chip coprocessor, drawing sheet 9 from US 2026/0330207 A1
Sheet 9 Routing medium workload math through an off chip coprocessor
How a helper chip takes over moderate AI math, drawing sheet 10 from US 2026/0330207 A1
Sheet 10 How a helper chip takes over moderate AI math
Sending direct access instructions to speed up AI calculations, drawing sheet 11 from US 2026/0330207 A1
Sheet 11 Sending direct access instructions to speed up AI calculations
How built in memory processors handle light text generation steps, drawing sheet 12 from US 2026/0330207 A1
Sheet 12 How built in memory processors handle light text generation steps
Passing grouped text analysis tasks to a dedicated nearby chip, drawing sheet 13 from US 2026/0330207 A1
Sheet 13 Passing grouped text analysis tasks to a dedicated nearby chip
Dividing complex language tasks between memory and helper units, drawing sheet 14 from US 2026/0330207 A1
Sheet 14 Dividing complex language tasks between memory and helper units
Offloading multiple text generation steps onto helper chips, drawing sheet 15 from US 2026/0330207 A1
Sheet 15 Offloading multiple text generation steps onto helper chips
Pairing smart memory rows with their own local calculating units, drawing sheet 16 from US 2026/0330207 A1
Sheet 16 Pairing smart memory rows with their own local calculating units
Distributing extra math circuits alongside each group of memory chips, drawing sheet 17 from US 2026/0330207 A1
Sheet 17 Distributing extra math circuits alongside each group of memory chips
Housing the secondary math unit directly inside the memory controller, drawing sheet 18 from US 2026/0330207 A1
Sheet 18 Housing the secondary math unit directly inside the memory controller
Linking individual smart memory units across a high-speed data switch, drawing sheet 19 from US 2026/0330207 A1
Sheet 19 Linking individual smart memory units across a high-speed data switch
Moving the secondary math unit into the central network switch, drawing sheet 20 from US 2026/0330207 A1
Sheet 20 Moving the secondary math unit into the central network switch
Adding math processors to removable memory cards, drawing sheet 21 from US 2026/0330207 A1
Sheet 21 Adding math processors to removable memory cards
Stacking smart memory dies vertically above an integrated logic base, drawing sheet 22 from US 2026/0330207 A1
Sheet 22 Stacking smart memory dies vertically above an integrated logic base
Connecting smart memory servers across a commercial cloud data center, drawing sheet 23 from US 2026/0330207 A1
Sheet 23 Connecting smart memory servers across a commercial cloud data center
Browse all the drawings 23 drawing sheets
Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.
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