AMD Files Patent for AI Chip Parts That Share Memory and Run Side by Side
AI chips can lose time doing two jobs one after the other. This filing, from AMD's Xilinx unit, lets the chip's processing cores work on both jobs at once while sharing a single block of memory.
What AMD's shared-memory AI chip actually does
Every time an AI chip has two jobs to finish, it can end up doing them one after the other, and all that waiting adds up. The filing's own background section calls this out: running two pieces of a program in sequence is slow.
The patent describes a fix. Instead of one worker per workstation, each small unit on the chip gets several processing cores and a block of memory they all share. Each core can take a different piece of the program and run it at the same time, and they can hand results to each other through that shared memory.
Since several cores now reach for the same memory, the design adds a kind of traffic cop (the patent calls it arbitration circuitry). It makes sure they take turns instead of trampling each other's data. You would never see any of this directly. It would show up, if at all, as AI work finishing sooner.
… first arbitration circuitry configured to synchronize access to the LDM by the processing cores.
Translation: A traffic controller manages how the processing cores share the local memory without crashing.
How the cores take turns at one memory
The patent describes a chip made of many small units, which it calls data processing elements (DPEs). When tuned for machine learning, they are called artificial intelligence engines. A configurable network of links and switches lets chosen units talk to one another.
Inside each unit sit multiple processing cores and one block of local data memory. The key piece is arbitration circuitry, a hardware referee that synchronizes access so two cores never write to the same memory at the same moment. The cores can run separate kernels (self-contained chunks of an application) in parallel and pass data to each other through that shared memory.
The filing also covers several add-ons:
- Extra arbitration so a unit's cores can reach the memory of a neighboring unit.
- Multiplexers (switches that let two signals share one wire) so both cores can use the same link to a neighbor.
- Broadcast circuits that send event signals, such as a read starting or a core stalling, to other units over a shared link.
One claimed version places a grid of these units inside a graphics processor, which hands tasks to the grid and gets results back.
… cores within a DPE may execute respective kernels of an application program in parallel, and may exchange data related to the kernels with one another via the LDM of the DPE.
Translation: Multiple computing engines run different parts of a program at the same time and share data through local memory.
Why waiting in line matters for AI chips
The practical payoff is speed. If two pieces of an AI workload can run side by side and swap data through nearby memory, the chip spends less time idle. That matters most in the places AI work piles up: data centers, graphics processors and the programmable chips Xilinx is known for.
The filing is about chip layout, not a finished product, and it names none. The claims cover a design where many units each hold several cores, with controlled sharing of memory between them and between neighbors. Whether that design shows up in shipping silicon is not something the document says.
AMD's 46th filing we've tracked since May in the AI chip wars adds to a run that includes one on network card failures and one on built-in manufacturing spares.
You will never see this feature. There is no setting, no icon and no new app. If it ever matters to you, it will be because an AI task on some device finished faster than it otherwise would have.
The idea answers a simple complaint: two jobs should not stand in line when the hardware could do them together. Giving cores a shared workspace and a referee is a sensible, practical way to do that.
The filing is short on numbers. It gives no speed gains and names no product, so any real benefit is still unproven. It reads as a routine engineering improvement from a chip team, and whether you ever feel it depends on whether it reaches products.
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The drawings
8 drawing sheets from US 2026/0310596 A1 · click any drawing to enlarge
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