Qualcomm Patents Chip Technology That Stops Unauthorized Programs From Reading Sensitive Data
Every time a chip touches a block of memory, something has to decide whether that access is allowed. Qualcomm's new patent describes a way to make those checks faster and more flexible on the type of processors that power most phones and connected devices.
How Qualcomm's memory permission lookup actually works
You're running several apps at once on your phone, and under the hood, each one is constantly reading and writing data in the chip's memory. The chip has to make sure none of those apps can snoop on memory that belongs to a different app or to the operating system itself. That gating process has to happen millions of times per second, so if it's slow or rigid, the whole device pays for it.
Qualcomm's patent describes a more flexible way to handle those checks. Instead of baking access rules directly into a big table (which wastes space and is hard to update), the system stores a small ID number in the table and then looks up the actual rules in a set of quick-access registers. Think of it like a coat-check ticket: the table just holds the ticket number, and the rules live somewhere much faster to reach.
This approach is aimed at RISC processors, the family of chip designs that underpins nearly every smartphone, tablet, and smart-home gadget. More flexible memory protection means it's easier to carve a chip into isolated zones, which is a building block for running sensitive code safely alongside everyday software.
performing, during physical memory access, a table walk to identify a leaf-node containing permissions for supervisor domains (SDs) corresponding to a physical memory address space; …
Translation: The chip checks memory permissions during a memory lookup to see what rules apply.
Inside the table-walk and programmable-register lookup
The patent centers on what chip engineers call a Memory Protection Table Extension (MPTE), a scheme for controlling which software components can read or write to which parts of physical memory on a RISC-based chip.
The process works in three steps:
- Table walk: When the chip needs to access a memory address, it traverses a tree-shaped data structure to find the relevant "leaf node," the entry that describes permissions for that address range. A leaf node is simply the final, most specific entry in the tree, like reaching the last folder in a nested file-system path.
- Read the ID field: Instead of storing the full permission rules inside the leaf node, the node contains a compact identification value. This keeps the table small and easy to cache.
- Register lookup: The chip takes that ID and looks up the actual access rules in a set of programmable registers (tiny, ultra-fast storage locations baked into the processor). The registers hold the concrete yes/no permissions for each supervisor domain, which are isolated software zones (think: the secure payment environment vs. The regular app environment).
By separating the address-to-ID mapping from the rules themselves, the design lets system software change permission policies for many memory regions at once simply by updating a register, without rewriting the entire table.
… performing a look-up to determine access permissions for the supervisor domains from a set of programmable registers according to an identification (ID) value from the access control permissions field of the leaf-node.
Translation: It consults a special register to verify if the program is allowed to read the requested data.
What this means for chip security on mobile and IoT devices
Memory isolation is one of the core building blocks of device security. If a malicious app can read memory it isn't supposed to touch, it can steal passwords, intercept messages, or tamper with other apps. On mobile and IoT chips, where dozens of processes run simultaneously, enforcing those boundaries efficiently matters a lot for both security and battery life.
Qualcomm's approach, if it works as described, could make it cheaper (in silicon area and in clock cycles) to support more supervisor domains on a single chip, which means more fine-grained isolation without a proportional cost. That's relevant for everything from flagship Android phones to the low-power RISC cores inside routers and wearables. Chip-level memory security is one of the faster-moving areas in Big Tech patent news, as companies race to harden processors against software-level attacks that hardware boundaries can stop cold.
The main claim here covers any method that checks a permission table, reads an ID from an end point, and then looks up rules from adjustable settings. That three-step pattern, written at such a general level, could block a wide range of competing chip designs, not just one specific circuit.
The saving grace is the language tying it to a specific class of low-power processors and a specific security layer. That keeps it from swallowing all of computing. Still, the core lookup pattern is broad enough to put a toll booth on something many chip makers already do.
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The drawings
10 drawing sheets from US 2026/0244579 A1 · click any drawing to enlarge
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