Intel Patents a GPU Memory System That Fetches Only the Texture Tiles a Scene Actually Needs
Every ray-traced frame asks a GPU to pull in enormous amounts of texture data, most of which never actually appears on screen. Intel's latest patent filing describes a memory system that only fetches the specific texture chunks a scene truly needs, using a shorthand label called a hash ID to find or create each chunk on demand.
How Intel's tiled texture trick cuts GPU memory waste
Modern games that use ray tracing look spectacular, but they come at a cost: the graphics chip has to juggle huge amounts of texture and scene data, much of it for parts of the image that are never rendered. Today's GPUs often load entire texture banks into memory just in case, which wastes space and slows things down.
Intel's patent describes a system where textures are broken into smaller tiles, and each tile gets a short, unique label called a hash ID. When a part of the graphics chip needs a particular tile, it sends a request with that label. A manager inside the chip checks whether the tile already exists in memory. If it does, it hands it over; if it doesn't, it carves out a fresh slot and attaches the same label for future requests.
The result is that only the texture tiles actually called for during rendering get loaded, rather than pulling in everything speculatively. Think of it like a library that prints a book only when someone checks it out, rather than stocking every possible title on the shelf.
How the hash ID request and tile allocation work together
The patent centers on what Intel calls a tiled resource: a large pool of graphics memory (textures, acceleration structures, and similar data) divided into discrete tiles rather than stored as one continuous block.
Each functional unit inside the GPU's execution hardware can issue a request for a specific tile. Instead of using a traditional memory address, the request carries a hash ID, a compact numerical fingerprint that uniquely identifies the tile being sought. A dedicated tiled resource manager intercepts every such request and does a quick lookup:
- If a tile matching that hash ID already exists, the manager returns a pointer to it immediately.
- If no matching tile exists, the manager allocates a new slot in the tiled resource pool, binds it to that hash ID, and hands the address back to the requesting unit.
The scheme is designed to integrate with ray-tracing workloads specifically, where rays scatter unpredictably across a scene and the set of textures any given frame touches is hard to predict in advance. By tying allocation to demand rather than pre-loading, the GPU avoids holding texture data in memory that no ray ever intersects.
The patent also covers the interface that connects the functional units to the tiled resource pool, suggesting Intel is thinking about this as a chip-level architectural feature rather than a software workaround.
What this means for ray-traced games and GPU efficiency
Ray tracing is the technique behind the realistic lighting in modern games and visual effects software, and it is notoriously memory-hungry. If a GPU has to pre-load every texture that might appear in a scene, you need enormous amounts of fast memory, which drives up hardware cost and power draw.
A demand-driven tile system like this could let Intel's future GPUs handle larger, more detailed scenes without requiring proportionally larger memory budgets. For you as a player or creative professional, the practical upside would be higher-quality visuals on cards that don't need record-breaking memory specs. Intel's sustained filing around ray-tracing efficiency suggests the company sees memory management as one of the remaining bottlenecks in closing the gap with its GPU rivals.
This is the 20th Intel filing we've tracked since May in the GPU rendering race, following one on filling dropped game frames and one on skipping redundant geometry.
The design saves memory by only creating pieces of a texture when a ray actually hits that surface, rather than loading everything upfront. The cost is a small delay every time a new piece has to be looked up or created mid-render, and in dense scenes where nearly every surface gets hit anyway, those delays add up without much memory benefit to show for them.
Whether that tradeoff is worth it depends entirely on how fast Intel can run the lookup step, and that speed is an engineering execution problem the patent itself does not answer.
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The drawings
125 drawing sheets from US 2026/0268578 A1 · click any drawing to enlarge
Show the other 52 sheets
Sheets 61 to 125 are in the full USPTO filing.
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