Nvidia · Filed May 12, 2025 · Published Nov 12, 2026

Nvidia Patents a Fix for Chip Traffic Jams That Leave Some Data Waiting Forever

Nvidia's filing describes a traffic rule for chip-to-chip links: keep some shared capacity in reserve, so a sender with tiny packets can't crowd out everyone else.

A computer chip and graphics chip share high-speed memory links designed to keep heavy data flows moving smoothly. Drawing from patent filing US 2026/0361665 A1.
A computer chip and graphics chip share high-speed memory links designed to keep heavy data flows moving smoothly.
See all 13 drawings from this filing ↓
Publication number US 2026/0361665 A1 US20260361665A1
Applicant NVIDIA Corporation
Filing date May 12, 2025
Publication date Nov 12, 2026
Inventors Naveen Kumar Narrishetti, Sathyanarayan Balaji, Kiran Kumar Muralidharan
US classification 370/422
Status when we published Waiting for an examiner (May 23, 2025)
Document 23 claims

What Nvidia's shared-credit reserve actually does

Every time one computer chip sends data to another, a tiny traffic cop decides whose packet goes out next. Each kind of traffic gets an allowance of credits, which work like permission slips from the receiving end: no credits, no sending.

To avoid giving every kind of traffic its own big waiting area, designers added a pool of shared credits. Nvidia's filing says that creates a trap. When the shared pool runs low and refills in dribbles, a sender with small packets grabs every scrap while senders with bigger packets wait indefinitely. The patent's fix is a reserve: the shared pool only opens up when it holds more than a set minimum, tied to the size of the largest packet. Below that line, everyone falls back on their own dedicated credits.

A second option protects time-sensitive traffic. In the filing's example, 10 of 100 shared credits are set aside for it and 90 go to everything else.

From the filing · CLAIM 1
… block one or more of the selected requests from being passed from the first-level arbitration logic to the second-level arbitration logic responsive to determining i) a lack of available shared credits in a shared credit pool, or ii) a lack of available dedicated credits assigned to the respective traffic type.

Translation: The system stops data packets when there are no credits left to send them.

How the credit check sits between two rounds

The patent covers the part of a chip's data link that decides which waiting packet goes out next. It uses two-level arbitration: level one picks a winner within each traffic type (reads, writes, completions), and level two picks the final winner across types.

Between the two rounds sits a credit check. Credits are permission slips from the receiving end, which has limited buffer space. Each traffic type gets dedicated credits, and all types can also draw on a shared pool, which saves chip area compared with a separate buffer per type. PCIe, a common connection standard, already uses shared credits.

The catch is starvation. In the filing's example, one client always asks for 2 credits while two others ask for 4. Once the shared pool refills in small amounts, the 2-credit client takes every refill and the others never get through. The fix: a request passes only if the shared pool is above a minimum (tied to the largest packet size) or it fits within that type's dedicated credits. Level two uses a Weighted Least Recently Used scheme (the sender who went longest ago, weighted, goes next).

An extra option splits shared credits by group: 10 of 100 for time-sensitive (isochronous) clients, 90 for the rest, with refills stopping once a group hits its share.

Why GPU and switch links could care about fairness

For you, the payoff would be invisible: fewer stalls when GPUs, network cards and switches shuffle huge amounts of data around, as they do in AI servers. A link that lets small, frequent requests crowd out big ones can leave parts of a system waiting, and this filing is a guard against that.

The filing says the idea works on PCIe, NVLink, Ethernet, InfiniBand and chip-to-chip links, and the claims name CPUs, GPUs, data processing units, network adapters and switches. It also says a single shared buffer can replace one buffer per traffic type to save chip area, and the reserve rule is what makes that trade safe. That is the strategic angle: cheaper chip space without letting some traffic get stuck.

Nvidia's 65th patent application we've tracked since July in our AI chip wars watchlist follows earlier filings on faster chatbot answers and running big models on less memory.

Editorial take

Claim 1 is wider than the headline idea. It describes a transmitter circuit with a checkpoint between two rounds of picking who sends next, and it holds back a request when either the shared credits or that sender's own credits run out. The claim never mentions the minimum reserve that the description is built around.

That reserve appears in the narrower claims, including the independent claim about a transmitter device, which spells out the exact test: pass if shared credits exceed a minimum, or if the packet fits within the sender's own allowance. So the broad claim covers the general shape, and the specific cure for starvation sits a layer down.

Either way, this is plumbing inside chips, and nobody will notice it working. Claim 23 names GPUs, network adapters and NVLink switches, so the rule is meant to travel across a lot of hardware.

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The drawings

13 drawing sheets from US 2026/0361665 A1 · click any drawing to enlarge

Reserving bandwidth keeps internal chip parts from stalling, drawing sheet 1 from US 2026/0361665 A1
Sheet 1 Reserving bandwidth keeps internal chip parts from stalling
Checking network capacity before sending data through a chip, drawing sheet 2 from US 2026/0361665 A1
Sheet 2 Checking network capacity before sending data through a chip
Giving each component its own private supply of transmission passes, drawing sheet 3 from US 2026/0361665 A1
Sheet 3 Giving each component its own private supply of transmission passes
How unreserved lanes leave big chip transfers stuck, drawing sheet 4 from US 2026/0361665 A1
Sheet 4 How unreserved lanes leave big chip transfers stuck
Saving minimum capacity stops data from getting stuck, drawing sheet 5 from US 2026/0361665 A1
Sheet 5 Saving minimum capacity stops data from getting stuck
Refilling transfer capacity based on who is waiting, drawing sheet 6 from US 2026/0361665 A1
Sheet 6 Refilling transfer capacity based on who is waiting
Halting outgoing requests until token reserves cross the safe threshold, drawing sheet 7 from US 2026/0361665 A1
Sheet 7 Halting outgoing requests until token reserves cross the safe threshold
Two connected devices managing traffic flow using token-checking logic, drawing sheet 8 from US 2026/0361665 A1
Sheet 8 Two connected devices managing traffic flow using token-checking logic
Show the other 5 sheets
Transmitting digital data across a channel using traffic-control checks, drawing sheet 9 from US 2026/0361665 A1
Sheet 9 Transmitting digital data across a channel using traffic-control checks
Computer components that coordinate graphics, memory, and networking, drawing sheet 10 from US 2026/0361665 A1
Sheet 10 Computer components that coordinate graphics, memory, and networking
Pairing multiple superchips to share data across high-speed links, drawing sheet 11 from US 2026/0361665 A1
Sheet 11 Pairing multiple superchips to share data across high-speed links
Linking a processor and graphics chip directly on one board, drawing sheet 12 from US 2026/0361665 A1
Sheet 12 Linking a processor and graphics chip directly on one board
Wiring eight AI chips together inside a high-powered server, drawing sheet 13 from US 2026/0361665 A1
Sheet 13 Wiring eight AI chips together inside a high-powered server
Browse all the drawings 13 drawing sheets
Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.
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