Intel · Filed Mar 28, 2025 · Published May 21, 2026 · verified — real USPTO data

Intel Patents On-Chip Security Channels for Trusted Execution Environments

When security protocols were designed for external PCIe devices, nobody fully accounted for the chips-within-chips world of modern processors. Intel's new patent tries to close that gap by bringing the same cryptographic handshakes used for external hardware to the devices baked directly into the CPU package.

Intel Patent: TEE Security for Integrated Processor Devices — figure from US 2026/0141123 A1
FIG. 1A — rendered from the official USPTO publication PDF.
Publication number US 2026/0141123 A1
Applicant Intel Corporation
Filing date Mar 28, 2025
Publication date May 21, 2026
Inventors Arie AHARON, Kapil SOOD, Rupin H. VAKHARWALA, Eric GEISLER, Tessil THOMAS, Shalini SHARMA, Lakshmi SRINIVAS, Asher ALTMAN
CPC classification 726/34
Grant likelihood Medium
Examiner CENTRAL, DOCKET (Art Unit OPAP)
Status Docketed New Case - Ready for Examination (Dec 8, 2025)
Parent application Claims priority from a provisional application 63723026 (filed 2024-11-20)
Document 20 claims

What Intel's integrated TEE security actually does

Imagine your laptop's processor is like a building. Over time, more and more rooms — a GPU, a network controller, a security chip — have been built inside that same building rather than as separate annexes. That's modern chip design. But the security system was originally designed to check IDs at the front door, not to verify the rooms inside.

Intel's patent describes a way to extend those same rigorous security checks — the kind used in confidential computing environments where sensitive data like health records or financial transactions must be protected — to integrated devices living inside the processor package itself.

The key idea is that a dedicated security engine inside the chip acts as a trusted middleman, establishing encrypted, authenticated communication channels with each on-chip device. So even if an attacker somehow compromised one part of the chip, they couldn't silently snoop on the others.

How Intel's SPDM engine secures on-chip endpoints

The patent describes a processor package — think of a single chip die or multi-die package — that includes a specially hardened security block called a root complex.

Inside that root complex sits two important pieces:

  • A Root of Trust (ROT) — a piece of circuitry whose identity and integrity can be cryptographically verified, forming the anchor for all security decisions on the chip.
  • An SPDM engine — SPDM stands for Security Protocol and Data Model, an industry standard (from DMTF) originally designed to authenticate and encrypt communication with external PCIe devices like GPUs or NICs. Think of it as TLS, but for hardware components.

The patent's core move is applying SPDM — previously an external-device protocol — to Root Complex Integrated Endpoints (RCiEPs). RCiEPs are devices that are physically inside the same chip package but logically appear to the system as if they were attached via PCIe. Things like integrated Thunderbolt controllers, on-die accelerators, or platform security processors fit this description.

By running full SPDM handshakes between the root complex and each RCiEP, the processor can verify that each internal device is genuine and untampered, then establish an encrypted channel — all before any sensitive workload data flows through.

What this means for confidential computing workloads

This patent is directly relevant to confidential computing — the practice of protecting data while it's being processed, not just while stored or in transit. Cloud providers and enterprise customers increasingly demand it for AI inference on sensitive data, secure enclaves, and multi-tenant hardware.

The weak link has been that even if external device attestation is solid, integrated on-chip peripherals were often implicitly trusted without formal verification. Intel's approach would let a Trusted Execution Environment (TEE) — like Intel TDX — formally attest not just the CPU cores, but every integrated device sharing the same silicon, tightening the security perimeter considerably for your most sensitive workloads.

Editorial take

This is unglamorous but genuinely important infrastructure work. The move from 'trust the chip as a whole' to 'cryptographically verify every component inside the chip' is where enterprise security is heading, and Intel filing this now signals they're building it into future silicon architectures, not bolting it on later. It's worth watching if you care about confidential AI or cloud security.

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Source. Full patent text and figures from the official USPTO publication PDF.

Editorial commentary on a publicly published patent application. Not legal advice.