Intel Patents a Compression Method That Makes Video Game Worlds Load Faster

By Patentlyze Team · Updated Jul 10, 2026

Ray tracing is one of the most memory-hungry parts of modern 3D rendering, and Intel thinks it has found a smarter way to store the geometric data that makes it work.

What Intel's adaptive bounding-box compression actually does

Imagine a 3D game rendering a detailed room. Before a beam of simulated light can bounce off a wall, the graphics chip has to check whether that beam hits anything in the scene. To speed that up, chips use invisible boxes called bounding boxes that wrap around every object, so the chip can quickly eliminate most of the scene and only check the stuff that actually matters.

The problem is storing those boxes takes memory, and memory bandwidth is expensive. Today, chips tend to allocate the same amount of storage precision for every box, regardless of its shape. Intel's patent describes a chip that can assign different levels of precision to each of the three spatial directions of a box independently, so a box that's very thin in one direction doesn't waste bits on fake precision there.

The result is that geometry data can be packed more tightly without meaningfully changing what the renderer sees. Think of it like compressing a photo: a mostly-sky image doesn't need as many bytes for the sky region as it does for a detailed face.

How the processor decides which dimensions get more bits

The patent describes processing circuitry that handles a data structure called a bounding volume hierarchy (BVH). A BVH is a tree of nested bounding boxes that the GPU walks during ray tracing to figure out which triangles a ray actually hits. The smaller and more accurate those boxes are, the faster and more correct the rendering.

Normally, each bounding box dimension (x, y, z) gets the same number of bits of storage precision through a process called quantization (basically, rounding continuous values down to a fixed set of discrete steps). Intel's approach breaks that assumption. The chip can dynamically allocate a different bit count per dimension, based on how much range that dimension actually needs to represent.

• A box that spans a large distance along the x-axis might get more bits for x to stay accurate.
• A flat box that barely extends along z might get fewer z bits, because coarse precision there has almost no visible effect.
• The allocation happens at runtime, not at compile time, so it adapts to whatever geometry is actually being rendered.

The practical effect is that BVH nodes can be stored in less memory or with less bandwidth, which matters a lot because reading BVH data is a major bottleneck in real-time ray tracing workloads.

What this means for ray tracing performance and memory

Ray tracing is the gold standard for realistic lighting in games and professional 3D tools, but it remains memory-intensive even on high-end GPUs. Anything that reduces how much data has to move between memory and the compute units translates directly to either faster frame rates or lower power consumption, and often both.

For Intel, which competes with Nvidia and AMD in the discrete GPU market through its Arc line, BVH efficiency is a real differentiator. Nvidia has published its own BVH compression research for years, so this patent signals that Intel is working at the same level of the stack. Whether or not this specific technique ships in a consumer product, it shows Intel's hardware team treating ray tracing architecture as a serious engineering priority rather than a checkbox feature.

Editorial commentary on a publicly published patent application. Not legal advice.