AMD · Chip · Filed Mar 20, 2025 · USPTO published Sep 24, 2026 · Sep 24 release

AMD Patents a Way to Trim GPU Memory Waste in Ray-Traced Games

Every ray-traced game secretly wastes GPU memory preparing for hardware it may never meet. AMD has filed a patent for a system that stops that from happening by giving each chip generation its own purpose-built code.

By Patentlyze Team · Updated Sep 24, 2026 · 3 min read

A scene with geometric objects and a corresponding bounding volume hierarchy (BVH) tree for efficient ray tracing. Drawing from patent filing US 2026/0289893 A1. — A scene with geometric objects and a corresponding bounding volume hierarchy (BVH) tree for efficient ray tracing.All 7 drawings ↓

Publication number: US 2026/0289893 A1(US20260289893A1)
Applicant: Advanced Micro Devices, Inc.
Filed · Published: Mar 20, 2025 · Sep 24, 2026
Inventors: Yue Zhuo, Zhen Hu
Status when we published: Examiner raised objections; the company can respond
Document: 20 claims
US classification: 345/426
Examiner: GOCO, JOHN PATRICK (Art Unit 2611)

What AMD's chip-tailored shader system actually does

Every time your GPU renders a ray-traced scene, tiny programs called shaders run thousands of times per second to calculate how light bounces around the screen. For years, one version of that code had to work on many different generations of AMD hardware, so it always reserved the maximum amount of memory any chip might need, even if your specific card needed far less.

AMD's new filing describes a system that instead pre-builds a separate shader version for each hardware generation. When your GPU starts up, the software picks the version that fits your exact chip, and it only sets aside as much memory as that chip actually uses. The result: less memory wasted sitting idle, and more left over for the game itself.

This is a behind-the-scenes optimization, not a new visual feature. You wouldn't see a new toggle in your graphics settings, but your GPU could be doing the same work while holding on to fewer resources, which in practice can mean better performance headroom.

From the filing · CLAIM 1

… selecting a shader program version based on a hardware version for the APD and on the operation provided by the application; and executing the selected shader program version.

Translation: Choosing and running a specific code version that matches the exact graphics hardware being used.

How the APD picks the right shader version at runtime

The patent describes a method for handling what AMD calls shader programs, small pieces of code that run on a GPU to calculate lighting, shadows, and reflections in real time. Ray tracing specifically (the technique that traces individual light rays to produce realistic reflections and shadows) relies heavily on these shaders.

Currently, a single "monolithic" shader program is written to serve multiple hardware versions. Because it has to be ready for any chip, it must reserve the maximum local memory (called local state storage) that the most demanding hardware version could ever require. Even on a simpler, older chip that needs much less, all that extra memory sits reserved and unused.

AMD's approach pre-compiles a distinct shader version for each hardware generation, each calibrated to that chip's actual memory needs. The selection step is critical: instead of the shader checking which chip it's on at the moment it runs (which still requires planning for the worst case), the right version is chosen before execution begins, based on a stored hardware version identifier.

The first independent claim covers three steps:

An application submits an operation to the GPU (referred to as an accelerated processing device, or APD)
The system selects the matching shader version based on the hardware version of that specific APD
The selected version executes, using only what that chip's generation actually needs

From the filing · THE ABSTRACT

… each shader program is tailored such that its associated set of local state does not exceed the amount actually needed by the corresponding hardware version.

Translation: Every program only saves the exact memory data required by that specific hardware model.

What this means for ray tracing on future AMD GPUs

Ray tracing is one of the most memory-hungry workloads a GPU handles. Any technique that cuts idle memory reservation directly frees up headroom for higher resolutions, more complex scenes, or better frame rates. For AMD, which sells GPUs across a wide range of generations simultaneously, a system that keeps each chip's shader footprint lean could be a meaningful efficiency gain across its whole product lineup.

For you as a player or developer, this is the kind of optimization that compounds. Games built on a graphics engine that uses AMD's tailored shaders could run with slightly lower GPU memory overhead, which matters most on mid-range cards where memory is tightest. AMD's long bet on ray tracing hardware makes this kind of plumbing work important to get right.

AMD's 13th filing we've tracked since June in the GPU rendering race builds on earlier applications like one on compressing game textures and one on wrapping 3D objects.

Editorial take

Claim 1 covers any system that reads a chip identifier, selects a pre-built program matched to that chip, and runs it. The claim sets no floor on how many chips must be supported, no rules about how those programs are built, and no constraints on what the identifier looks like, so its reach extends well beyond AMD's own software.

That breadth has real consequences. Any tool or middleware that chooses a leaner, chip-tailored program instead of a one-size-fits-all version would need to clear this claim to operate freely, because the claim requires nothing more than that exact selection step.

The engineering logic behind it is sound: a program that reserves the largest possible memory budget for every chip wastes resources on chips that never need it. Solving that by picking a smaller, purpose-built program per chip is a simple fix, and Claim 1 essentially wraps a fence around that fix in its entirety.

Source: US 2026/0289893 A1 at the USPTO (PDF). Full patent text and figures are in the official publication.

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