Intel Patents a GPU Scheduling Trick That Stops Threads From Stepping on Each Other
When two threads inside a GPU try to read from the same memory slot at the same moment, one has to wait. Intel's new patent tries to stop that waiting before it starts.
What Intel's cache bank scheduling actually fixes
Today's graphics chips run thousands of small tasks at once, and they all need to fetch data from memory. The problem: that memory is divided into sections called "banks," and if two tasks try to hit the same bank at the same time, one has to sit and wait. Those wait times add up fast inside a chip doing millions of operations per second.
Intel's patent describes a way to schedule tasks so they spread out across different memory banks at the same time, the way a grocery store tries to keep every checkout lane busy rather than queuing everyone into one. The chip's scheduling circuit looks ahead at which bank each task needs before it decides who runs next, then picks a set of tasks that won't collide.
There's a second idea layered on top: "early dependency clearing." Normally, a task has to wait for data to fully arrive before the chip marks it as free to continue. Intel wants to mark it free earlier, during the trip to memory, so other work can proceed while the data is still in transit.
… select a plurality of the threads available for scheduling based on the banks to be accessed by the threads, including to select threads that are to access different banks of the cache …
Translation: The chip picks tasks that use separate memory lanes so they can run at the same time without traffic jams.
How the GPU picks threads to avoid bank collisions
The patent covers a GPU built around two related ideas.
Bank-aware thread scheduling works like this: a GPU cache (fast on-chip memory) is divided into multiple banks, each of which can serve only one request at a time. When the scheduler picks which threads (mini-tasks) to run next, it checks which bank each thread needs. It then deliberately selects a group of threads that will each hit a different bank, so every memory request can proceed in parallel with no collisions. The claim covers the circuitry that does this: it determines the target bank for each candidate thread, then selects across different banks before issuing the schedule.
Early dependency clearing addresses a separate bottleneck. Chips track which tasks depend on which data using a scoreboard, essentially a to-do list that marks a task blocked until its required data arrives. Normally a task stays blocked until the load completes. Intel's approach clears that block earlier, before the data is fully back, so downstream tasks can start queuing up and the chip wastes fewer cycles waiting.
- Cache banks are checked before threads are picked, not after.
- Thread selection explicitly targets inter-bank diversity.
- Scoreboards release dependencies during the load, not after it.
Bank aware thread scheduling and early dependency clearing techniques are described herein.
Translation: The patent describes a method for organizing tasks to prevent memory bottlenecks and speed up processing.
What this means for GPU chip design going forward
Bank conflicts are one of those unglamorous chip problems that erode the performance numbers GPU makers promise on spec sheets. Every stalled cycle inside a GPU is a cycle that isn't rendering a frame, running an AI model, or processing sensor data. Intel targeting this at the scheduler level, in hardware, means the fix applies to every workload automatically without software developers having to think about memory layout.
Claim 1 is deliberately broad: it covers any GPU with a multi-bank cache and circuitry that selects threads by their target bank. That breadth matters because it could apply to general compute GPUs, not just graphics pipelines. Intel's push into discrete GPU territory (its Arc line) and AI accelerators makes that scope relevant to this week's Big Tech patents, which show several chip-company filings aimed at squeezing more work from the same silicon area.
This is the 28th Intel filing we've tracked since May in the AI chip wars, building on one on skipping AI steps and one on splitting work across chips.
Claim 1 covers selecting which thread to run based on which memory bank it needs to access, then scheduling that thread accordingly. That description contains no limits on chip type, number of banks, or hardware generation, meaning the claim draws a circle around a behavior rather than a specific design. A claim that broad, if granted, could give Intel a say over any processor that picks threads with memory-bank conflicts in mind, which is a common problem in parallel computing hardware generally.
The early dependency clearing idea, where the hardware stops blocking other operations before a memory read fully completes rather than after, is the narrower and more technically specific piece of this filing, and it is the part most likely to survive scrutiny and deliver real performance gains in memory-heavy workloads.
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The drawings
31 drawing sheets from US 2026/0252384 A1 · click any drawing to enlarge
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