Qualcomm Files Patent to Pre-Arrange AI Data So Phone Chips Load It Faster
Before your phone's AI can do any math, its data has to be lined up just right, and Qualcomm has filed a patent application on lining it up ahead of time. The trick packs two tiny numbers into one slot so the chip can load a whole block at once.
What Qualcomm's AI data-packing patent does
A warehouse worker receives a pallet of boxes in no particular order. Before a single one can go on a shelf, she spends the afternoon sorting them. Your phone's AI chip faces a version of this every time it runs a model on your device.
Qualcomm's patent application tackles that sorting job by doing it ahead of time. The numbers that make up an AI model, called weights, are shrunk into small whole numbers and rearranged into blocks that match the chip's built-in math unit. Two of the shrunken 4-bit numbers share one slot, so a whole block loads in a single step.
The payoff is that the chip gets its data already in the order it needs and can get on with the math. You would never see any of this, but it is part of what decides how fast and how efficiently AI runs on a phone.
obtain a first matrix of quantized values, wherein the first matrix of quantized values includes integer values in a portion of a first row linearized from a first two-dimensional sub-tile of a second matrix of floating-point values …
Translation: The chip takes floating point numbers and converts them into simplified integers arranged in a specific order.
How Qualcomm tiles weights to fit the chip
The claims describe a way to prepare and use matrices (grids of numbers) for AI math. It starts with a grid of floating-point values (precise decimal numbers), such as a model's weights. The grid is cut into small two-dimensional sub-tiles (little rectangles), each flattened into a row of a new grid, then quantized, meaning converted into compact whole numbers. A dependent claim names 4-bit integers.
Two 4-bit values are half the size of one 8-bit value, so the description packs two into a single slot: one sub-tile in the lower bits, the next in the upper bits. That lets one load instruction fill a whole tile of the chip's array register (the working memory of its matrix unit). The chip then unpacks the values into separate rows. The tile size follows the register's width, which differs from chip to chip. Because a model's weights are fixed, this prep can be done once, ahead of time.
The other side of the multiplication holds activations (values that change as the model runs). Those are flattened in column-major order (reading down the columns) and quantized on the fly. In the 8-bit example, one tile of weights plus two sub-tiles of activations means three loads feed four multiply instructions. The filing also describes a version that multiplies the grid by a single vector, which it ties to generating text one token at a time.
… performing a matrix operation using the portion of the first row, the portion of the second row, the first sub-tile of quantized values, and the second sub-tile of quantized values to generate an output matrix …
Translation: It crunches the prearranged data chunks together to produce the final calculation results.
Why on-device AI speed depends on data layout
If you use AI features on your phone, such as summarizing text or editing photos, the speed and battery cost come down to how efficiently the chip handles grids of numbers. This filing targets one small piece of that: getting the data into the matrix unit already lined up, so the chip spends less time reshuffling and more time calculating.
The filing says the layout is tuned to each device's working-memory size, which varies between chips. That means one AI model could be prepared for many different devices. For Qualcomm, it describes a way to get more out of the matrix hardware the filing assumes, in a device where compute, memory and power are all tight.
Qualcomm's 59th filing we've tracked in the AI chip wars since July builds on ideas like skipping redundant chip work and shrinking shared AI models.
This filing sits close to the ground. The claims describe no new hardware. They cover how software should arrange a model's numbers so an existing matrix unit, the part of a chip built for grid math, can take them in big gulps.
That puts it near the shippable end of the scale. Preparing the model's fixed numbers happens once, ahead of time, and the live step only reshuffles the changing inputs as the model runs. The shortest route to a product is a model-conversion tool that does the packing, paired with a chip that already has the matching instructions.
The catch is that the layout depends on the size of each chip's working memory, so each device needs its own version of the packed model. Expect it to stay invisible to you. If it works, a phone assistant answers a bit sooner and uses a bit less battery.
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The drawings
11 drawing sheets from US 2026/0329965 A1 · click any drawing to enlarge
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