Intel Patents a System for Splitting AI Work Across Different Chips Automatically
Most AI systems run on one type of chip, but real servers often mix CPUs, GPUs, and specialized accelerators. Intel's new patent describes a way to automatically split AI workloads so each piece lands on the device best suited to run it.
How Intel wants to spread AI tasks across mixed chips
Today, running a large AI model on a mix of different chips requires engineers to manually figure out how to divide the work, a slow and error-prone process that leaves a lot of hardware sitting idle.
Intel's patent describes a system that handles that division automatically. It reads information about every chip in a machine, then breaks the AI task into smaller pieces and assigns each piece to the chip best equipped to handle it. Think of it like a restaurant dispatcher who knows every cook's specialty and routes each order to the right station without anyone having to ask.
The result is that mixed hardware setups, which are common in data centers and research labs, could run AI workloads more efficiently without needing hand-tuned configuration for every new model or chip combination.
converting, based on device information about a plurality of heterogeneous devices, a SD graph representing the DL workload into a MD graph including a plurality of sub-graphs that respectively represent a plurality of DL sub-workloads to be assigned to DL stages on the plurality of heterogeneous devices …
Translation: The system analyzes different types of hardware to break a large AI task into smaller pieces that each chip can handle.
How Intel's graph-splitting system assigns work to each chip
The patent centers on a concept called heterogeneous sharding, which means cutting an AI model into pieces (shards) sized and shaped for different kinds of processors working together. Today's AI frameworks generally assume all chips are alike; this system does not.
The process works in two main steps:
- Graph conversion: The AI workload is represented as a single-device (SD) graph, a map of all the computations the model needs to perform as if one device will do everything. The system reads the specs of every available chip and converts that map into a multi-device (MD) graph, which breaks the original map into sub-graphs, one for each chip or chip group.
- Stage assignment: Each sub-graph is then assigned to a specific DL stage (a step in the AI processing pipeline) on its target device, so the chips can work in sequence or in parallel without duplicating effort.
The system uses device information (memory size, compute speed, connection bandwidth) to decide where each piece of work goes. That means a CPU-heavy sub-task stays on the CPU, a matrix-heavy sub-task goes to the GPU, and a specialized accelerator handles whatever it does best, all without a human engineer manually writing that routing logic.
What this means for AI servers running mixed hardware
Data centers running large AI models rarely have identical hardware throughout. They mix older GPUs with newer ones, pair CPUs with dedicated AI accelerators, and bolt on new chips as they become available. Right now, getting a model to use all that hardware well requires significant manual tuning every time something changes. A system that automates the routing decision could cut setup time and squeeze more output from hardware that would otherwise sit partially idle during inference or training runs. For you as an end user, faster or cheaper AI inference is the downstream effect, even if you never see the machinery behind it.
Intel has strong motivation here: the company sells both CPUs and AI accelerators (its Gaudi line), and a software layer that makes mixed Intel hardware work together efficiently would make those chips a more attractive package. Chip-level workload routing is one of the more active areas in this week's Big Tech patents, as hardware makers try to build software moats around the silicon they sell.
Intel's 26th filing we've tracked since May in the AI chip wars continues a pattern of splitting AI work across chip types, following one on runtime memory splitting and one on training across chips.
If this system works as described, the person who benefits most is the infrastructure engineer who currently spends days hand-tuning how a model distributes across a server rack full of mismatched chips. Automating that routing logic removes a real bottleneck, especially as hardware configurations grow more varied. The patent covers the architectural idea at a high level, so whether Intel's implementation actually beats manual tuning in real deployments remains to be seen, but the problem it addresses is concrete and costs real money today.
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The drawings
14 drawing sheets from US 2026/0244488 A1 · click any drawing to enlarge
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