Xilinx Patents an ML System That Sorts Chip Test Results Automatically
Verifying a chip design means running thousands of tests and then manually sorting the results, a process so tedious that engineers often automate pieces of it with brittle, hand-written rules. Xilinx's new patent hands that sorting job to a machine learning model instead.
How Xilinx's circuit testing shortcut actually works
An engineer sits down after a long overnight chip test run and stares at a spreadsheet of thousands of raw numbers. Each number represents some behavior the chip did or did not exhibit, and someone has to decide what each result means before the team can declare the chip ready.
That sorting step is what Xilinx wants to automate here. Instead of a human (or a fixed script) deciding which test results go into which bucket, a machine learning model reads the results and assigns them automatically. The idea is that the model learns what a "good" result looks like versus a suspicious or failing one, then tags each data point accordingly.
For chip designers, this could mean faster feedback after each test run and fewer hours spent on what is essentially data-entry work. You would still write the tests; the system just handles the paperwork that comes after.
… running a regression test on the circuit design using a verification testbench to generate test results and sampled values for the coverpoint variables; classifying, by a machine learning model, the sampled values of the coverpoint variables for the regression test based on the test results; …
Translation: An artificial intelligence model sorts test data based on how the circuit performed.
How the ML model bins coverpoint values after a regression run
The patent describes a four-step process for automating what chip engineers call functional coverage, which is the discipline of tracking whether a design has been tested in every scenario that matters.
- Define valid ranges: The system first figures out the legal value ranges for each coverpoint variable (a measurable signal or parameter in the chip design) based on the constraints the engineer has already specified.
- Run regression tests: A standard verification testbench (a simulation harness that exercises the chip against a suite of test cases) runs and produces two things: pass/fail results and the actual values each coverpoint variable took on during the run.
- ML classification: A machine learning model reads those sampled values alongside the test results and classifies each data point. The model is making a judgment about what each observed value means in the context of whether the test passed or failed.
- Bin assignment: The system then sorts every sampled value into one of several predefined buckets, called bins, which represent categories of coverage. Coverage data, the final output, is produced from these assignments.
The key shift is replacing hand-coded binning logic with a trained model that can generalize across different designs and test configurations.
Coverage data for the regression test is generated by the computer hardware by assigning the sampled values of the coverpoint variables to different ones of a plurality of bins based on the classifying.
Translation: The computer organizes the sorted test results into specific categories to measure performance.
What this means for chip verification teams
Functional coverage is one of the most labor-intensive parts of chip development. Engineers traditionally write explicit rules describing what counts as "covered" for every signal they care about, and then they manually audit whether those rules fired during testing. As chips grow more complex, that rule-writing scales badly. A model-driven approach could absorb some of that complexity without requiring engineers to enumerate every possible case.
Xilinx, now part of AMD, focuses on FPGAs (chips that can be reprogrammed after manufacture), where verification is especially demanding because the chip's behavior changes with each new customer design loaded onto it. Automating coverage analysis fits AMD's broader push to speed up the design-to-silicon pipeline, and this filing sits alongside other chip-design interesting tech patents that signal how much AI tooling is moving into the engineering workflow itself.
AMD's 49th filing in the chip patents we've tracked since May follows one on accurate AI math and one on faster data conversion.
The core trade AMD is making here is replacing human-written rules with a machine learning model to decide whether a chip test has actually covered the ground it was supposed to cover. That buys flexibility and speed, but it surrenders something engineers have always relied on: a clear, readable explanation for why any given result landed where it did.
A wrong call here does not just produce a bad report. It can give a team false confidence that a chip is ready to ship when it is not, and AMD sells chips into cars, aircraft, and financial systems where that mistake cannot be fixed with a software update.
The patent says nothing about how the model is trained or how it performs on chip designs it has never encountered before. Those are not minor footnotes, and until there are clear answers to both, the efficiency argument is real but incomplete, and the trade does not yet read as worth it.
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The drawings
9 drawing sheets from US 2026/0252774 A1 · click any drawing to enlarge
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