Nvidia Patents a Technique That Cuts Delay When Cameras Process Video
Nvidia wants the chip that processes your camera footage to start working before an entire frame has even arrived, cutting the delay between capture and display down to nearly nothing.
What Nvidia's frame-slicing approach actually does
Every time a camera snaps a frame of video, something has to process that raw image data before you see a clean, usable picture. That job falls to a dedicated chip called an image signal processor (ISP). Normally the ISP waits for a complete frame to arrive before it starts working, which creates a small but real delay.
Nvidia's patent describes a way to break each frame into horizontal strips, called slices, so the ISP can start processing the top of the image while the camera is still capturing the bottom. The key insight is that the strip heights aren't fixed. The system reads the camera's settings and the ISP chip's speed, then figures out the exact strip sizes that let processing run in tight parallel with capture.
The result is that the ISP finishes its work much sooner after capture ends, because it has a head start on most of the frame. For video pipelines where every millisecond counts, like live streaming, robotics, or automotive cameras, that head start adds up.
… determining, based on the camera configuration information and the ISP clock speed, a first slice pixel height for one or more first slices of a video frame to be captured by the camera system and a last slice pixel height for a last slice of the video frame …
Translation: The system calculates the exact size of image segments based on how fast the camera hardware is running.
How the ISP calculates slice height from clock speed
The patent describes a pipeline that divides each incoming video frame into a series of horizontal strips before the image signal processor touches them. Most strips have the same pixel height (called the first slice pixel height), but the final strip at the bottom of the frame is allowed to be a different height (the last slice pixel height). That asymmetry matters because it lets the system fit the slices cleanly into the frame without leftover pixels.
The slice heights are not guessed or set by a user. The system calculates them automatically from two inputs:
- Camera configuration information, things like the frame resolution, pixel clock rate, and line timing that describe how the sensor delivers data
- ISP clock speed, how fast the image signal processor chip can actually crunch pixel data
By matching slice size to both the camera's output rate and the ISP's processing rate, the system ensures the ISP can finish each slice before the next one arrives. That means processing and capture overlap in time rather than running back-to-back.
Latency (the gap between when a frame is captured and when a finished image is ready) shrinks because the ISP is never sitting idle waiting for a full frame to land. The patent is aimed at the kind of embedded camera pipelines found in autonomous vehicles, drones, AR hardware, and high-frame-rate industrial systems.
Systems and methods for reducing image signal processor (ISP) latency in video acquisition and processing pipelines. In at least one embodiment, processing circuitry is provided in a video acquisition and processing pipeline to perform intelligent slicing of video frames for reducing ISP latency.
Translation: Nvidia is using a technique that breaks video frames into smaller pieces to help the processor handle data faster.
What this means for cameras in Nvidia-powered devices
Latency in camera pipelines is one of those problems that sounds invisible until it isn't. In a self-driving car or a drone, a few milliseconds of extra delay between what the camera sees and what the computer acts on can matter. In AR headsets, lag between the real world and the overlay makes the experience feel broken. Nvidia's framing of this patent is squarely aimed at those high-stakes, real-time use cases.
Nvidia makes the chips and systems-on-chip that power many of those applications, from Jetson embedded modules to automotive SoCs. A patent on adaptive ISP slicing fits neatly into that product range, where squeezing latency out of the camera pipeline is a real engineering priority. Coverage of this kind of hardware-level camera work sits alongside many other new Big Tech patents in the chip and embedded-vision space that are reshaping how devices see the world.
The real problem is how easily the setup can break. Slice heights must be calculated correctly before every recording session, and swapping cameras mid-stream forces those numbers to update, with no backup plan if something goes wrong. That is a lot of places for things to fail.
For cars and augmented-reality glasses, though, the trade-off makes sense. Slow image processing has direct safety and usability costs in those products. Moving the tricky slice-sizing math into the chip itself keeps that burden away from the rest of the software.
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The drawings
10 drawing sheets from US 2026/0245341 A1 · click any drawing to enlarge
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