AMD · Chip · Filed May 22, 2026 · USPTO published Sep 24, 2026 · Sep 24 release

AMD Files Patent for a Processor Grid Where Chips Share Memory With Their Neighbors

Most chips waste time and power shouting data across long wires. This AMD Xilinx patent describes a grid of small processors that simply read and write each other's memory directly, cutting out the middleman entirely.

By Patentlyze Team · Updated Sep 24, 2026 · 3 min read

A grid of four data processing elements (DPEs) with cores and memory modules, showing data flow between them. Drawing from patent filing US 2026/0288358 A1. — A grid of four data processing elements (DPEs) with cores and memory modules, showing data flow between them.All 25 drawings ↓

Publication number: US 2026/0288358 A1(US20260288358A1)
Applicant: Xilinx, Inc.
Filed · Published: May 22, 2026 · Sep 24, 2026
Inventors: Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Tim Tuan, Ralph D. Wittig, David Clarke, Goran H.K. Bilski, Kornelis A. Vissers, Richard L. Walke, Christopher H. Dick, Zachary Dickman, Philip B. James-Roxby, Peter McColgan
Status when we published: Waiting for an examiner
Document: 21 claims
US classification: 711/148
Parent application: Continuation of 18/636,005 (filed Apr 15, 2024)(18636005)

How Xilinx's neighbor-sharing chip grid actually works

Today, when processors inside a chip need to pass data to each other, they typically send it through a shared communication bus or interconnect, a kind of highway that can get congested and slow things down. AMD's Xilinx division has filed a patent describing a different approach: arrange many small processors in a grid, and let each one directly access the memory sitting inside its immediate neighbors.

Think of it like a neighborhood where each house leaves its garage unlocked so the people next door can grab tools without anyone having to drive across town. Each processor in the grid has its own core and its own memory, but the cores around it can read and write that memory as if it were their own.

The goal is faster, more direct data flow inside the kinds of chips used for AI processing, signal processing, and other jobs that move huge amounts of data in tight patterns. Less waiting, fewer hops, more throughput.

From the filing · THE ABSTRACT

Each core may be configured to communicate with other neighboring data processing engines of the plurality of data processing engines by shared access to the memory modules of the neighboring data processing engines.

Translation: Each processor can talk to its neighbors by directly using their memory modules.

How each engine core reaches into a neighbor's memory

The patent describes a device built from many data processing engines (DPEs), each one a pairing of a compute core and a local memory module. These engines are laid out in rows, forming a 2D array.

The key mechanism is shared memory access between neighbors: instead of sending a message across a network-on-chip (a chip's internal postal system), a core can directly read or write the memory module sitting inside an adjacent engine. This is sometimes called shared scratchpad access, where scratchpad refers to fast, software-managed memory that sits close to the compute logic.

This design is closely related to Xilinx's AI Engine architecture, already found inside their Versal family of chips. In that architecture, a large array of cores handles signal processing and machine-learning workloads, and the engines communicate by passing data through adjacent memory tiles rather than routing it over a slower interconnect.

The practical effect is that data-heavy algorithms, things like matrix multiplications for AI inference or fast Fourier transforms for radio signals, can be tiled across the grid and pass intermediate results to neighbors with very low delay and low energy cost.

What shared-memory processor grids mean for AI chips

For you as a consumer, this is the kind of architecture that ends up inside chips powering 5G base stations, data center AI accelerators, and edge computing hardware. Faster, lower-power data movement inside the chip means devices that process more information without running hot or draining energy budgets.

For the semiconductor industry, a patent covering the arrangement of processing engines and their shared-memory communication could be broad enough to touch a wide class of spatial computing designs, including competitors building similar processor arrays for AI workloads. That scope is worth watching, even if claim 1 of this specific publication has been canceled, which limits its immediate legal reach.

AMD's 38th filing we've tracked since May in our AI chip competition watchlist follows the self-scheduling GPU filing and one redirecting spare storage for AI.

Editorial take

The core of this filing describes a grid of processing engines where each unit shares direct access to its neighbors' memory, letting them pass data back and forth without going through a central switchboard. Claim 1 covers that arrangement at a fairly high level of abstraction, which means the protection, if granted, would attach to the organizing principle rather than any specific wiring or chip material.

That breadth matters because it could cover a wide range of hardware layouts built around the same neighbor-to-neighbor memory sharing idea, not just one exact chip design.

All claims are listed as canceled, though, which means this filing currently enforces nothing. The specification still stands as a detailed public record of the architecture, and AMD may well be pursuing the same ideas in a related filing with revised claims, but as written there is no live protection to license or assert.

Source: US 2026/0288358 A1 at the USPTO (PDF). Full patent text and figures are in the official publication.

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