Nvidia Files Patent for Letting Its Graphics and Support Chips Share Data
The chip in your phone, laptop or car often holds a graphics core plus small specialists that can't read each other's notes. Nvidia's patent adds a translator so one note works for all of them.
What Nvidia's shared-pointer patent does
Ever handed a document to a coworker who uses a totally different filing system? You jot down where it lives, and they have no idea what your note means. A version of that happens inside modern chips.
Many chips pack a graphics processor next to specialist engines for video, camera images and AI. Each engine speaks its own software language. When the graphics processor saves some data and writes down its location, the other engines can't read that note, so programmers end up writing extra translation code for each one.
Nvidia's patent adds a translator layer. When a program saves data, a single location note is created and automatically mapped so every engine on the chip can use it. You would write code for the graphics processor only, and the other engines follow along.
circuitry to generate one or more first pointers usable by one or more first accelerators to access data stored in storage allocated by one or more second accelerators …
Translation: Special circuitry creates pointers so one chip can access data stored by another chip.
How the callback translates one pointer
The patent covers a way for a graphics processor (GPU) and other processing engines on one chip to share stored data. When the GPU saves data, it creates a pointer, a short note saying where the data lives. Engines such as a deep learning accelerator, a vision accelerator, an image signal processor or a video compositor run different software, so they normally can't read that note.
The fix is a software callback, a small piece of code that runs automatically at the right moment and translates between engines. A manufacturer or programmer registers a list of parameters for each engine, covering things like:
- Memory registration (how to claim and release data)
- Task submission (how to hand the engine a job)
- Error checking
In practice, the program makes its usual memory request (the filing names cudaMalloc as one example). The callback maps the GPU's pointer to the matching entries for each other engine, so each one can read or write the same data. Tasks go into one command stream (a single to-do queue), and the callback translates each task for the engine that handles it.
The claims cover this as processor circuitry, as a method and as a system on a chip. A third engine can work in parallel on the same pointers. The filing also describes a fallback where programmers write their own translation code when no callback exists.
… a pointer generated for a first accelerator is mapped to a pointer for a second accelerator so that the second accelerator may utilize the pointer for the first accelerator to access stored data.
Translation: A pointer from one chip is translated so another chip can use it to reach stored data.
Why fewer lines of code matter for chips
If you like fast photo, video and driver-assist features, the payoff is mostly behind the scenes. Developers could write one version of their code instead of one per engine, which usually means fewer bugs and quicker feature launches. The filing's own example is a driving system: the GPU hands video compression to one engine, object spotting to a second and collision prediction to a third.
The description says chips like this could sit in desktops, laptops, tablets and mobile devices, and it leans on Nvidia's own CUDA toolkit as the home for the idea. That ties extra engines to software developers already know, which gives them one more reason to keep building on Nvidia's platform.
Nvidia's 51st filing we've tracked since July in the AI chip wars watchlist continues a thread started with one on sharing math tasks and one on splitting GPU work.
This filing sits close to shippable. The description leans on software: a mapping layer that a chipmaker or programmer registers, plus an existing memory call that gets extended to trigger it. No new silicon is described.
What has to exist first is the hardware itself. The chip needs a graphics processor plus engines for video, camera or AI work, and each engine needs its own mapping written and tested. That is slow, careful work, and it is where the schedule would live.
The shortest route to a product is a driver and developer toolkit update on chips that already carry those engines. You would never see it directly. You would just see apps that behave better and arrive sooner, if developers take to it.
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The drawings
28 drawing sheets from US 2026/0319843 A1 · click any drawing to enlarge
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