Google Files Patent for AI Chips That Add Up Numbers Before Multiplying Them
Google's AI chips spend most of their energy multiplying numbers, so this patent asks a sneaky question: what if you rarely had to multiply at all? By adding first and multiplying once per group, it shrinks a 20,480-step job to just 15 multiplications.
What Google's add-first chip math actually does
Imagine you're a cashier ringing up a cart with 20,000 items, and the price tags come in only 15 different values. You wouldn't punch in every item one at a time. You'd sort the items into 15 piles by price, add up each pile, and multiply once per price.
That is the idea in this Google patent application, built into the circuitry of an AI chip. AI models do mountains of multiplication, and multiplying is one of the most power-hungry things a chip can do. Many modern models also round their internal numbers to tiny whole numbers, so only a handful of distinct values exist.
Google's design keeps a small cheat sheet that says which pile each number belongs to. Each tick of the chip's clock handles one pile: it adds up the matching numbers and does a single multiplication. The result is the same answer with far less work.
A matrix multiplication operation is factorized into a plurality of clock cycles to obtain partial products, each clock cycle corresponding to a factor group of activation values associated with a distinct non-zero weight value.
Translation: Math operations are broken down into steps mapped to specific clock cycles.
How the chip sorts numbers by weight each cycle
The circuit takes in a list of input numbers (an activation vector, such as pixel values from an image) and a column of quantized weights, which are a model's learned numbers rounded to small whole numbers. With 4-bit weights, each one is a value from 0 to 15.
The trick is regrouping. The filing's example rewrites 3a0 + 6a1 + 6a2 + 2a3 + 4a4 + 5a5 + 3a6 as a3·2 + (a0 + a6)·3 + a4·4 + a5·5 + (a1 + a2)·6, cutting 7 multiplications to 5. At full scale, 20,480 inputs need only 15. Each clock cycle (one tick of the chip's timer) handles one weight value:
- A memory stores a bit vector for each weight: a row of 15 on/off flags with one switched on, marking the cycle that weight belongs to.
- AND gates (simple on/off switches) pass only the inputs matching the current cycle and block the rest.
- An adder tree (layers of adders that combine numbers in pairs until one total remains) sums the passed inputs.
- One multiplier applies the weight value, and an accumulator keeps a running total.
The filing also describes skipping cycles for weight values that never appear, compressing the stored flags with run-length encoding, and duplicating the circuit to handle several columns at once. A reuse scheme called common subexpression elimination could cut operations by up to about 50% in one example.
Why cheaper AI math matters for your devices
If you use AI on a phone, or just rely on AI services running in a data center, the cost that matters is energy per answer. Power and heat limit how fast chips can run, and multiplication is a big part of both. The filing says this design lowers energy per inference and fits more throughput into each square millimeter of silicon compared with multiplication-heavy accelerators.
There is a catch. The payoff is biggest with very small weights: 4-bit weights need 15 cycles, while 8-bit weights would need 255. The filing also says the memory can be fixed in read-only form for one specific model, which trades flexibility for efficiency. It is a patent application, so it describes a design, not a product.
Google's 22nd filing we've tracked since July in the AI chip wars watchlist builds on keeping camera AI ready and offloading memory work.
You are unlikely to ever see this on a spec sheet. If it works as described, you would notice it as an AI feature that answers a bit faster, a device that stays cooler under load, or cloud AI that costs less to run.
The benefit depends on models using small, rounded weights, which the filing calls a growing trend. At 4 bits the savings are dramatic, and at 8 bits the cycle count climbs to 255, so your gain would shrink for models that need more precision.
Overall this is a clean piece of chip arithmetic with a clear payoff: less energy for the same answer. The best version of it stays invisible to you, and you just get an assistant that wastes less power.
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The drawings
6 drawing sheets from US 2026/0319741 A1 · click any drawing to enlarge
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