Intel Files Patent to Run Visual AI on Fewer Stored Building Blocks
Image-recognition AI is already squeezed down to plus-or-minus-one values. This Intel filing squeezes it again by giving each layer a short menu of patterns to pick from, then building a chip that looks up answers instead of redoing the math.
What Intel's shared pattern menu actually does
You snap a photo and your phone instantly spots the faces in it. Behind that tiny moment, an image-recognition AI is running millions of small calculations, and each one costs memory, battery and time.
Engineers already shrink these models by boiling each of the AI's filters down to a grid of plus ones and minus ones. A common 3-by-3 filter then has 512 possible patterns. Intel's filing says that is still more than you need. Each layer of the AI would get a short menu of patterns, and every filter would only store a ticket number saying which one it picked.
Because the menu is short, the chip can work out each pattern against a patch of the image once, write the answers in a table, and let every filter look its answer up. The filing says the company's experiments showed no loss of accuracy compared with the plus-or-minus-one models.
… a kernel pattern buffer to buffer a 1-bit convolutional kernel subset for the convolutional layer of the CNN model, wherein the 1-bit convolutional kernel subset includes 2 τ 1-bit convolutional kernels with a size of K×K …
Translation: The hardware stores a specific group of simplified building blocks to process images efficiently.
How the chip looks up answers instead of recomputing
The filing covers two linked pieces: a way to shrink a trained image model, and an accelerator (a chip block built to run AI) that takes advantage of the shrinking. In a convolutional neural network (an AI model that scans images), each layer slides small grids of numbers called kernels, K by K cells in size, across the picture.
In the quantization step (turning precise numbers into coarse ones), every kernel becomes a grid of +1 and -1 values. Normally any of 2 to the power of K×K patterns is allowed. Here each layer gets a subset of just 2 to the power of τ patterns, with τ smaller than K×K, so a kernel needs about τ bits (the 1s and 0s computers store) instead of K×K. The filing describes choosing the subset with a selection matrix, optionally paired with a permutation matrix (a way of reordering the candidates) learned during training.
The accelerator in claim 21 has five parts:
- Input buffer: holds the image.
- Weight buffer: holds the kernel indexes, the ticket numbers.
- Kernel pattern buffer: holds the 2 to the power of τ menu patterns.
- Processing engine array: several nodes, each handling a region of the image.
- Output buffer: collects the results.
In the filing's example node, a dot product unit (multiplies and adds an image patch against a pattern) scores every menu pattern once and writes the results into a lookup table. Accumulators then add up the looked-up answers for each output channel. A plus-or-minus-one model repeats that work for every output channel, while this one repeats it only for each menu pattern, which the filing says is far fewer.
The disclosure relates to fractional-bit network quantization and deployment of CNN models.
Translation: This patent covers a technique for shrinking artificial intelligence models so they run on lighter hardware.
Why smaller image AI matters for low-power devices
The practical stake is running image AI on devices with limited memory and battery. The filing names mobile, embedded and other low-power devices as the reason people shrink these models at all, and says this approach compresses a model by roughly the number of cells in a kernel divided by τ, compared with the plus-or-minus-one version.
For you, that would show up indirectly, as camera and recognition features that need less power. The filing mentions FPGAs (chips that can be reprogrammed after they are made) as one place the design could run. A patent is not a product, so nothing here says when or whether it ships, and the accuracy claim comes from the company's own experiments.
This is the 53rd Intel filing we've tracked in AI chip wars since May, following applications on resuming giant calculations and rearranging data on the fly.
Claim 21 covers any chip that stores a deliberately limited menu of binary filter patterns, where the menu size is mathematically capped below the total number of cells in the filter grid. Five physical components are named, but the legal weight sits in that size restriction and nothing else.
The claim says nothing about how many calculating units the chip contains, how the short menu gets built, or where the chip ends up. A camera, a phone processor, and a data-center card could all fall inside the claim as long as their filter menus follow that specific formula.
If granted, Intel could challenge any chip using that shortened-menu structure regardless of surrounding design choices. Accuracy guarantees and lookup details appear only in dependent claims, which carry far less legal force, so the core claim is broad enough to matter across a wide range of products.
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9 drawing sheets from US 2026/0340367 A1 · click any drawing to enlarge
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