Intel · Filed Jun 27, 2026 · Published Oct 22, 2026

Intel Files Patent for Giant Calculations That Pick Up Where an Interruption Left Off

Intel is describing a chip instruction for giant math jobs that can be stopped mid-way and later continue from the exact spot it left off, instead of starting over.

A processor tracks progress during massive math problems so it can pause and resume without losing its place. Drawing from patent filing US 2026/0329584 A1.
A processor tracks progress during massive math problems so it can pause and resume without losing its place.
See all 16 drawings from this filing ↓
Publication number US 2026/0329584 A1 US20260329584A1
Applicant Intel Corporation
Filing date Jun 27, 2026
Publication date Oct 22, 2026
Inventors Edward T. GROCHOWSKI, Asit K. MISHRA, Robert VALENTINE, Mark J. CHARNEY, Simon C. STEELY JR.
US classification 712/208
Status when we published Waiting for an examiner (Jul 14, 2026)
Parent application is a Continuation of 19004194 (filed 2024-12-27)
Document 20 claims

What Intel's pause-and-resume matrix math does

A computer is partway through a huge calculation that will take hours. Then something small interrupts it: a memory page isn't ready, or the operating system needs the chip for something else. On most hardware, that kind of stop can mean throwing away the work and starting again.

Intel's filing describes a chip that keeps its place. When the interruption hits, the chip writes down a progress marker showing how much of the multiplication is done and saves the partial results. When the job restarts, it reads the marker and carries on.

The math in question is matrix multiplication, the grid-times-grid arithmetic behind AI, graphics and scientific software. The patent notes these jobs can be so large that they would run for hours, days or even a month on an ordinary processor.

From the filing · CLAIM 1
… a two dimensional array of multiplier-adder circuits to multiply each matrix tile of the first plurality of matrix tiles with a corresponding matrix tile of the second plurality of matrix tiles to generate a corresponding result matrix tile …

Translation: A grid of math circuits multiplies large blocks of data together all at once.

How Intel's chip saves its place in a big job

The filing covers a chip with a dedicated accelerator (a helper circuit built for one kind of math) that sits next to the regular processor cores. The cores run one set of instructions, while the accelerator runs its own set to multiply large grids of numbers, called matrices.

The accelerator splits each big matrix into smaller, non-overlapping blocks called tiles. An instruction tells the chip the dimensions of those tiles. A two-dimensional array of multiplier-adder circuits (small units that multiply two numbers and add the result to a running total) then multiplies matching tiles and builds up the answer tile by tile.

The earlier filings in this family centered on the completion progress indicator, a stored number showing how far the multiplication got before an interruption. The description gives a simple formula built from three loop counters, and says restarting reverses the formula to recover where the job stopped. It also says the indicator can be meaningless to software, because only the chip needs to understand it.

The description adds a few extras:

  • Tiles can be nested, so smaller tiles fit the chip's small, fast caches (nearby memory).
  • Full tiles run on a fast path; partial tiles after a page fault or restart run on a slower path.
  • The chip can store which tiling method it used so it resumes the same way.
From the filing · THE ABSTRACT
… store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

Translation: It saves your exact spot when paused so the system can resume the massive calculation later.

Why a resumable calculation matters for AI chips

If you use anything that leans on heavy matrix math, from AI tools to scientific software, the benefit is work that isn't wasted. A long job that gets bumped by the operating system doesn't have to restart from zero, which saves time and electricity.

For Intel, the filing is about making matrix math a dependable, built-in chip feature rather than something software has to babysit. This is a continuation of an older family going back to 2016, so it extends an existing idea rather than announcing a new product. Note that the claims here focus on the accelerator and tile layout, while the interruption idea comes from the shared description.

Intel's 52nd filing we've tracked in the AI chip wars since May follows work on rearranging data on the fly and auditing chips behind AI decisions.

Editorial take

If you've ever lost an hour of progress to a crash, you already understand the appeal. A chip that saves its place means a long calculation survives the ordinary hiccups of a busy computer, and you'd notice it only as a job that finishes when it should.

The benefit lands mostly on people running very large jobs, such as AI training or scientific simulations, and much less on someone browsing the web. For them, restarting a day-long calculation is a real cost, and this removes it.

The claims in this latest filing center on the tiled accelerator hardware, so the resume feature is background here rather than the headline. It's a sensible, practical piece of chip plumbing, and most readers will never see it directly.

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The drawings

16 drawing sheets from US 2026/0329584 A1 · click any drawing to enlarge

A computer chip tracking calculation progress to handle pauses, drawing sheet 1 from US 2026/0329584 A1
Sheet 1 A computer chip tracking calculation progress to handle pauses
Saving partial math progress when an interruption strikes, drawing sheet 2 from US 2026/0329584 A1
Sheet 2 Saving partial math progress when an interruption strikes
Basic input data and progress markers for large calculations, drawing sheet 3 from US 2026/0329584 A1
Sheet 3 Basic input data and progress markers for large calculations
Adding memory spacing details to the calculation inputs, drawing sheet 4 from US 2026/0329584 A1
Sheet 4 Adding memory spacing details to the calculation inputs
How the chip runs math blocks and records progress, drawing sheet 5 from US 2026/0329584 A1
Sheet 5 How the chip runs math blocks and records progress
Breaking massive data grids into tiny bite-size pieces, drawing sheet 6 from US 2026/0329584 A1
Sheet 6 Breaking massive data grids into tiny bite-size pieces
Switching speeds depending on how much data is ready, drawing sheet 7 from US 2026/0329584 A1
Sheet 7 Switching speeds depending on how much data is ready
Three different chip designs built to handle the calculations, drawing sheet 8 from US 2026/0329584 A1
Sheet 8 Three different chip designs built to handle the calculations
Show the other 8 sheets
How a chip reads and runs program commands, drawing sheet 9 from US 2026/0329584 A1
Sheet 9 How a chip reads and runs program commands
Inside a processor core built to run heavy math commands, drawing sheet 10 from US 2026/0329584 A1
Sheet 10 Inside a processor core built to run heavy math commands
Combining multiple computing cores and memory controls on one chip, drawing sheet 11 from US 2026/0329584 A1
Sheet 11 Combining multiple computing cores and memory controls on one chip
Connecting a main processor to memory and external devices, drawing sheet 12 from US 2026/0329584 A1
Sheet 12 Connecting a main processor to memory and external devices
Linking two processors directly together to share memory and data, drawing sheet 13 from US 2026/0329584 A1
Sheet 13 Linking two processors directly together to share memory and data
Routing external devices directly into two interconnected processors, drawing sheet 14 from US 2026/0329584 A1
Sheet 14 Routing external devices directly into two interconnected processors
Packing an entire computer system onto a single silicon chip, drawing sheet 15 from US 2026/0329584 A1
Sheet 15 Packing an entire computer system onto a single silicon chip
Translating software instructions so they can run on different chips, drawing sheet 16 from US 2026/0329584 A1
Sheet 16 Translating software instructions so they can run on different chips
Browse all the drawings 16 drawing sheets
Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.
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