Qualcomm · Filed Feb 20, 2025 · Published Aug 20, 2026 · verified — real USPTO data

Qualcomm Patents a Way to Let Memory Chips Handle Multiple Jobs at Once

Qualcomm is patenting a way for memory chips to pause one job, save its place, and switch to another without losing any work, much like a computer's operating system does for software, but built directly into hardware.

Processor connected to memory chips featuring internal computing units for parallel processing. Drawing from patent filing US 2026/0244482 A1.
Processor connected to memory chips featuring internal computing units for parallel processing.
See all 8 drawings from this filing ↓
Publication number US 2026/0244482 A1
Applicant QUALCOMM Incorporated
Filing date Feb 20, 2025
Publication date Aug 20, 2026
Inventors Subbarao Palacharla, Pan Deng, Rui Cao, Pankaj Deshmukh, Jungwon Suh
CPC classification 712/228
Grant likelihood Medium
Examiner ABAD, FARLEY J (Art Unit 2181)
Status Non Final Action Mailed (Aug 4, 2026)
Document 20 claims

How Qualcomm's in-memory multitasking actually works

Every time your phone runs a navigation app, plays music, and checks your email at the same time, several processors are competing for the same memory. That memory has to serve all of them without dropping the ball.

Qualcomm's patent describes a system where the memory chip itself acts as a kind of traffic coordinator. When one processor's task gets interrupted, the chip saves a snapshot of exactly where that task was, tucks it away inside the memory bank, and lets another processor's task run. When it's time to return, the chip pulls that snapshot back out and picks up right where things left off.

The goal is to stop processors from stepping on each other's work when they all share the same physical memory. Instead of each processor managing this juggling act on its own, the memory chip handles it internally, which could make the whole system faster and less wasteful.

From the filing · CLAIM 1
… saving, by the memory controller, the first PIM context associated with the interrupted execution of the first task to a memory bank of the PIM device; and restoring, by the memory controller using the first PIM context saved to the memory bank, execution of the first task on the first virtual PIM.

Translation: The memory controller saves the current state of a paused task directly into the memory chip so it can resume later.

How the memory controller saves and restores each task's state

The patent covers a processing-in-memory (PIM) device, which is a chip that can do some computing work inside the memory itself rather than shipping data back and forth to a separate processor. That round-trip normally eats up time and power, so keeping computation local is a meaningful efficiency gain.

The twist here is multi-context support. A "context" in chip design means the complete saved state of a running task (think of it as a bookmark that captures every register value and in-progress calculation). Normally, if you have several processors sharing one PIM chip, they need to coordinate carefully so they don't overwrite each other's work.

Qualcomm's approach creates virtual PIMs (isolated slices of the physical chip, one per connected processor). Each processor thinks it has its own dedicated memory compute unit. The memory controller handles the reality:

  • Interrupts a task when it's time to switch
  • Receives the task's context from that processor
  • Saves the context into a reserved memory bank on the chip
  • Runs the next task from a different processor
  • Restores the saved context and resumes the first task later

The context switching protocol (the rulebook that decides when and how to hand off) lives in the memory controller, keeping the connected processors largely unaware of the scheduling complexity underneath.

From the filing · THE ABSTRACT
Systems, methods, devices, and apparatuses are disclosed for supporting and efficiently switching between multiple contexts associated with multiple system-on-a-chip (SoC) clients in a processing-in-memory (PIM) architecture.

Translation: This patent describes a way for memory chips to juggle tasks from several different processors at the same time.

What this means for chips running AI on a single device

On-device AI is pushing more and more processors onto a single chip package. Qualcomm's own Snapdragon platforms, for example, pack a CPU, GPU, and a dedicated AI engine onto one piece of silicon, and all of them want to read and write memory constantly. Without a coordination layer, they waste time waiting on each other or, worse, corrupt each other's in-progress work.

This patent puts that coordination inside the memory hardware rather than piling more software overhead onto each processor. For device makers building phones, laptops, or edge AI hardware, that distinction matters: software-based scheduling adds latency and burns battery, while a hardware solution handles it invisibly and faster. Engineers working on PIM architectures for inference accelerators will find this filing directly relevant, and it sits alongside a broader wave of new Big Tech patents targeting in-memory compute as the next front in the fight to shrink AI's power bill.

Qualcomm's 34th filing we've tracked since July in the AI chip wars space builds on one letting phones report AI capacity and one sharing memory processing across tasks.

Editorial take

When many processors on the same chip fight over the same shared memory, the device gets slower and burns more power. The more specialized chips you cram in, the worse the fighting gets.

Moving traffic management into the memory controller itself targets the exact spot where the fighting breaks out. That match between cause and fix is what sets this design apart.

Anyone who has watched a phone or laptop suddenly slow down under a heavy load will recognize why this matters. The problem and the solution finally sit in the same place.

There are more where this came from

We read every patent application Big Tech publishes and send you the ones worth knowing. Plain English, free, every week.

The drawings

8 drawing sheets from US 2026/0244482 A1 · click any drawing to enlarge

Patent filing page

Source. Full patent text and figures from the official USPTO publication PDF.