AMD Patents Technology to Redirect Unused Storage Space Toward AI Processing
Cache memory normally has one job: speed up data fetch for the main processor. AMD is patenting a way to temporarily steal that space and hand it directly to an AI accelerator sitting on the same chip cluster, no extra memory needed.
How AMD's chiplets borrow their own cache for AI jobs
Every time a chip runs an AI task, it needs a place to scribble down its working numbers. Usually that means dedicated memory, which costs silicon space and power. AMD's new patent describes a different approach: let the chip borrow from memory it already has.
Modern AMD chips are built from small interconnected tiles called chiplets. One of those chiplets sits between the main processor and the computer's main memory, acting as a go-between. It contains a pool of fast temporary storage called cache. AMD's idea is to let an AI chip on that same chiplet reach into the cache and use a section of it as its own private scratch pad when it needs extra room.
The system can carve out a slice of the cache for the AI accelerator on demand, then give it back when the job is done. You wouldn't flip a switch yourself. The chip handles the negotiation internally, and the goal is faster AI processing without bolting on extra memory hardware.
… reconfiguring at least a first sub-portion of the first portion of the cache from being used as a cache to be used as directly-accessible memory, wherein the accelerator is configured to perform machine learning operations and to store input operands and output results into the directly-accessible memory …
Translation: It switches part of the temporary storage chip into working memory for AI tasks.
How the accelerator reclaims cache space at runtime
The patent describes a method for dynamically reconfiguring part of a chiplet's cache to act as directly-accessible memory (sometimes called scratchpad memory, meaning the AI chip can read and write to specific addresses there directly, without going through the usual cache-management rules).
Here is the sequence the patent outlines:
- A chiplet that sits between the graphics accelerator and main system memory normally handles caching operations, storing recently used data so the processor can grab it fast.
- When an on-chip AI accelerator needs more working memory than it has, it sends a request to reconfigure part of that cache pool.
- The system marks a portion of the cache as directly-accessible memory, and the AI accelerator stores its input data and output results there instead of reaching out to slower main memory.
- When the AI task finishes, that memory region can revert to standard cache duty.
The key detail is the phrase "explicitly requesting" in the claim. Unlike a cache, which moves data in and out automatically based on what the processor needs, the AI accelerator asks for specific addresses by name. That gives it predictable, low-latency access, which matters when you are feeding data through a neural network layer by layer.
The patent also notes that the two chiplets involved can be separate physical dies, meaning this approach works across the multi-tile chip designs AMD already ships.
… performing machine learning operations with the first sub-portion by a machine learning accelerator within the first chiplet.
Translation: A dedicated processor chiplet uses this newly converted space to run AI computations.
What this means for AI performance in AMD's future chips
For everyday users, the practical upside is that AI tasks running on AMD hardware could get done faster without the chip needing an additional dedicated memory chip soldered nearby. That matters for laptops and compact desktops where space and power budgets are tight. If the AI accelerator can grab fast, local memory on demand rather than waiting on slower system RAM, inference tasks (running an AI model to get an answer) finish in fewer milliseconds.
The broader story is about chip design efficiency. AMD's run of chiplet-architecture filings shows the company leaning hard into making each tile do double duty. Squeezing more function out of existing silicon, rather than adding more of it, is what keeps chips competitive as they get harder and more expensive to manufacture at smaller scales.
AMD's 36th filing we've tracked since May in the AI chip wars watchlist, following one compressing GPU data and one cutting vision model compute, continues the pattern of squeezing more from less.
If you have ever watched an AI tool on your laptop slow to a crawl mid-task, this patent is aimed at that exact moment. AMD is designing chips where the fast, expensive memory normally reserved for the main processor can be temporarily handed off to the AI engine when it needs a burst of speed, then handed back.
The honest limit is that sharing anything between two demanding systems creates conflict, and the filing does not fully explain what happens when both sides want that memory at once. That gap matters, because a bad answer there means stutters and slowdowns rather than the smooth experience the architecture promises.
Even so, the design is detailed enough to show AMD is solving a real bottleneck rather than reserving a vague idea. If they get the handoff logic right, the person who benefits is anyone running an AI assistant, editing photos, or transcribing audio locally, who currently just waits.
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The drawings
6 drawing sheets from US 2026/0288661 A1 · click any drawing to enlarge
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