AMD
AMD · Chip · Filed Dec 29, 2025 · USPTO published Nov 12, 2026 · This week's release
AMD Patents an AI Math Circuit That Feeds Its Own Answers Back In
AI chips usually keep separate hardware for grid math and list math. AMD's patent application describes one block that does both by feeding its own answers back in as new inputs.
- Publication number
- US 2026/0359386 A1(US20260359386A1)
- Applicant
- ADVANCED MICRO DEVICES, INC.
- Filed · Published
- Dec 29, 2025 · Nov 12, 2026
- Inventors
- Stuart David Simpson Biles, Brian William Thompto, Michael Estlick, Glendon Leo Akins III, Douglas John Cutter, Mahadev Deshpande
- Status when we published
- Waiting for an examiner
- Document
- 20 claims
- US classification
- 708/520
- Parent application
- Claims priority from a provisional application 63771554 (filed Mar 13, 2025)
What AMD's reuse-your-answer math circuit does
Ever had to grab one gadget for chopping and a different one for slicing, when a single good knife could do both? AI chips face a version of that. The math behind AI mostly falls into two buckets: multiplying big grids of numbers (matrices) and combining simple lists of numbers (vectors). Chips have traditionally used one dedicated block for each.
AMD's patent application describes a single block of small calculators, laid out in rows and columns, with selector switches wired to them. A switch can take the answer from one step and feed it straight back in as the next step's input.
Different instructions tell the switches to pick different sequences. The same hardware can then handle grid-by-grid, grid-by-list, and list-by-list math. Along the way, it skips the extra trip of saving every in-between answer to a register or memory.
… a first multiplexor configured to select, based on a first instruction, a first sequence of vector inputs for the plurality of arithmetic elements.
Translation: A switch inside the chip chooses which data flows back into the math units next based on program instructions.
How the selector switches pick the next inputs
At the center is a matrix engine, a block of circuitry that does the multiply-and-add math behind AI models. The patent's example is a 4 by 4 grid of 16 arithmetic elements (tiny calculators that multiply two numbers and add the result to a running total).
The twist is a pair of multiplexers (switches that pick one of several data sources). Each calculator stores its latest result in a register with read ports (outputs) wired to those switches. Based on the instruction, a switch can feed the next step from the input registers or from a chosen row or column of the grid. One step's answer becomes the next step's input with no trip to memory.
The description leans on a math fact: multiplying two matrices can be built from a series of outer products (each multiplies a column of numbers by a row of numbers), added together. Different instructions run different sequences, so the same hardware covers:
- Matrix times matrix
- Matrix times vector (a vector is a single list of numbers)
- Vector times vector
- Flipping a matrix on its side (transposition), shuffling rows and columns, and finding the largest or smallest values
The claims cover the engine, a processing system with memory and a processor, and a method.
… one or more multiplexors that are able to, based on an instruction, select one or more of the arithmetic elements to provide output data as the input data for a subsequent operation.
Translation: The routing circuit feeds calculation results right back into the math engine as inputs for the very next step.
Why one shared circuit conserves processor resources
For you, the payoff would be indirect, since this is a chip-level design idea. The filing lists desktops, laptops, servers, smartphones, game consoles and tablets as devices that could carry the processor. If one block can handle several kinds of math, a chip could do AI work with fewer separate pieces and less effort spent shuttling in-between answers around.
The filing ties the design to x86 processors and an extension it calls Advanced Computation Extension, which adds tile registers (two-dimensional storage for numbers) and matrix instructions alongside the existing AVX vector instructions. That places the idea inside the CPU's own instruction set, where software can ask for these operations directly.
AMD's 50th filing we've tracked since May in our AI chip wars watchlist follows one on adjusting chatbot guesses and one on routing custom models faster, adding to a picture of how the company is shaping its AI chip work.
Source: US 2026/0359386 A1 at the USPTO (PDF). Full patent text and figures are in the official publication.
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The drawings · 7 sheets
7 drawing sheets from US 2026/0359386 A1 · click any drawing to enlarge
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